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Design Entry

AC107: HDL Methodology Offers Fast Design Cycle and Vendor Independence App Note	24 KB	4/1996	Click on the to rate this document
AC108: Implementing Multipliers with Actel FPGAs App Note	84 KB	4/1996	Click on the to rate this document
AC110: Synchronous Dividers in Actel FPGAs App Note	38 KB	4/1996	Click on the to rate this document
AC111: Three-Stating Actel Device I/O Pins for Board Level Testing App Note	26 KB	4/1996	Click on the to rate this document
AC117: Using FPGAs for Digital PLL Applications App Note	26 KB	4/1996	Click on the to rate this document
AC119: Implementing Three-State and Bidirectional Buses with Multiplexers in Actel FPGAs App Note	58 KB	4/1997	Click on the to rate this document
AC120: Designing FIR Filters with Actel FPGAs App Note	74 KB	6/1997	Click on the to rate this document
AC122: Optimal Datapath Generation Using ACTgen App Note	124 KB	6/1997	Click on the to rate this document
AC128: Design Techniques for RadHard FPGAs App Note	64 KB	9/1997	Click on the to rate this document
AC130: Designing State Machines for FPGAs App Note	86 KB	9/1997	Click on the to rate this document
AC137: Integrating Multiple CPLD Functions in an Actel SX Device App Note	31 KB	3/1999	Click on the to rate this document
AC145: Power-Up and Power-Down Behavior of 54SX and RT54SX Devices App Note	79 KB	1/2001	Click on the to rate this document
AC147: Using the BUFD and INVD Delay Macros App Note	78 KB	3/2001	Click on the to rate this document
AC151: Termination of the Vpp and Mode Pin for RH1020 and RH1280 Devices in a Radiation Environment App Note	49 KB	10/2001	Click on the to rate this document
AC160: IEEE Standard 1149.1 (JTAG) in the SX/RTSX/SX-A/eX/RT54SX-S Families App Note	568 KB	10/2002	Click on the to rate this document
AC163: Axcelerator Carry-Connect Macros App Note	121 KB	1/2003	Click on the to rate this document
AC164: Axcelerator Family Memory Blocks App Note	155 KB	1/2003	Click on the to rate this document
AC165: Introduction to Actel FPGA Architecture App Note	55 KB	1/2003	Click on the to rate this document
AC169: Using A54SX72A and RT54SX72S Quadrant Clocks App Note	596 KB	2/2003	Click on the to rate this document
AC175: Axcelerator Family PLL and Clock Management App Note	179 KB	6/2003	Click on the to rate this document
AC178: Optimal Usage of Global Network Spines in ProASIC^PLUS Devices App Note	618 KB	7/2003	Click on the to rate this document
AC182: Axcelerator I/O Selection Guide App Note	371 KB	8/2003	Click on the to rate this document
AC183: Using Global Resources in Actel's Axcelerator Family App Note	126 KB	8/2003	Click on the to rate this document
AC198: Clock Skew and Short Paths Timing App Note Information about calculating clock skew in Actel FPGAs	150 KB	3/2004	Click on the to rate this document
AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note	115 KB	3/2004	Click on the to rate this document
AC207: Global Clock Networks in Actel Antifuse Devices App Note	191 KB	6/2004	Click on the to rate this document
AC218: Using Axcelerator RAM as Multipliers App Note	390 KB	2/2005	Click on the to rate this document
AC219: Using ProASIC^PLUS RAM as Multipliers App Note	337 KB	2/2005	Click on the to rate this document
AC249: I/O Features in Axcelerator Family Devices App Note Relative Pin Locations (ZIP, 341 KB, 11/04)	1.2 MB	1/2006	Click on the to rate this document
AC281: ProASIC^PLUS RAM/FIFO Blocks App Note	229 KB	8/2006	Click on the to rate this document
AC306: Using ProASIC^PLUS Clock Conditioning Circuits App Note	354 KB	9/2007	Click on the to rate this document
AC308: Metastability Characterization Report for Actel Antifuse FPGAs App Note	116 KB	10/2007	Click on the to rate this document