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Design Entry
AC362: SmartFusion cSoC: Programming FPGA Fabric and eNVM Using In-Application Programming Interface App Note
Design Files
(ZIP, 24 MB, 1/12)
3 MB
1/2012
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AC360: SmartFusion cSoC : Implementation of FatFs on Serial Flash App Note
Design Files
(ZIP, 17.9 MB, 1/12)
Programming Files
(ZIP, 305 KB, 1/12)
926 KB
1/2012
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AC346: SmartFusion cSoC : Loading and Booting from External Memories App Note
Design Files
(ZIP, 32.4 MB, 1/12)
Programming Files
(ZIP, 40.9 KB, 1/12)
1 MB
1/2012
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AC348: SmartFusion cSoC: Accessing External Memories Using the External Memory Controller App Note
Design Files
(ZIP, 5.4 MB, 1/12)
Programming Files
(ZIP, 50 KB, 1/12)
748 KB
1/2012
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AC347: SmartFusion cSoC: Interfacing with OLED using I2C App Note
Design Files
(ZIP, 20.7 MB, 1/12)
Programming Files
(ZIP, 59.9 KB, 1/12)
580 KB
1/2012
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AC345: SmartFusion cSoC: Accessing EEPROM Using I2C App Note
Design Files
(ZIP, 5.4 MB, 1/12)
Programming Files
(ZIP, 27.9 KB, 1/12)
668 KB
1/2012
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AC343: Accessing Serial Flash Memory Using SPI Interface App Note
Design Files
(ZIP, 15.7 MB, 1/12)
Programming Files
(ZIP, 58.4 KB, 1/12)
672 KB
1/2012
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AC336: Designing a High-Speed Timer in SmartFusion Fabric App Note
Design Files
(ZIP, 15.4 MB, 1/12)
Programming Files
(ZIP, 168 KB, 1/12)
769 KB
1/2012
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AC339: Interrupting SmartFusion MSS Using FABINT App Note
Design Files
(ZIP, 28.8 MB, 1/12)
Programming files
(ZIP, 299 KB, 1/12)
625 KB
1/2012
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AC335: Building an APB3 Core for SmartFusion cSoC FPGAs App Note
Design Files
(ZIP, 15.9 MB, 1/12)
1 MB
1/2012
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AC338: Interrupting SmartFusion MSS Using GPIO and FABINT App Note
Design Files
(ZIP, 23.1 MB, 1/12)
Programming files
(ZIP, 240 KB, 1/12)
379 KB
1/2012
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AC333: Connecting User Logic to the SmartFusion Microcontroller Subsystem App Note
Design Files
(ZIP, 25.5 MB, 1/12)
1 MB
1/2012
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AC363: SmartFusion cSoC: Achieving Maximum Throughput From FPGA Master to MSS Peripherals App Note
Design Files
(ZIP, 20.6 MB, 1/12)
2 MB
1/2012
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AC198: Clock Skew and Short Paths Timing App Note
Information about calculating clock skew in Actel FPGAs
860 KB
6/2011
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AC361: SmartFusion: FPGA Fabric Synthesis Guidelines App Note
801 KB
1/2011
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AC270: SPI Flash Emulation for Fusion Devices Design Example App Note
Design Files
(ZIP, 9 KB, 03/10)
519 KB
3/2010
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AC327: UART-to-SPI Interface Design Example App Note
Design Files
(ZIP, 375 KB, 04/09)
500 KB
4/2009
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AC326: GPIO Expansion Using UART Design Example App Note
Design Files
(ZIP, 4.9 MB, 04/09)
501 KB
4/2009
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AC269: Implementing an OLED Controller Parallel Interface Design Example App Note
Design Files
(ZIP, 609 KB, 04/09)
482 KB
4/2009
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AC268: Using IGLOO and ProASIC3 FPGAs as a System Power Sequencer Design Example App Note
Design Files
(ZIP, 3 MB, 04/09)
1,002 KB
4/2009
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AC265: Clock Generation and Distribution Design Example App Note
Design Files
(ZIP, 192 KB, 04/09)
531 KB
4/2009
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AC257: Microcontroller I/O Expander Design Example App Note
Design Files
(ZIP, 1.8 MB, 04/09)
458 KB
4/2009
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AC308: Metastability Characterization Report for Actel Antifuse FPGAs App Note
114 KB
10/2007
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AC306: Using ProASIC
PLUS
Clock Conditioning Circuits App Note
345 KB
9/2007
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AC281: ProASIC
PLUS
RAM/FIFO Blocks App Note
223 KB
8/2006
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AC249: I/O Features in Axcelerator Family Devices App Note
Relative Pin Locations
(ZIP, 341 KB, 11/04)
1 MB
1/2006
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AC218: Using Axcelerator RAM as Multipliers App Note
381 KB
2/2005
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AC219: Using ProASIC
PLUS
RAM as Multipliers App Note
329 KB
2/2005
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AC207: Global Clock Networks in Actel Antifuse Devices App Note
186 KB
6/2004
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AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note
112 KB
3/2004
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AC183: Using Global Resources in Actel's Axcelerator Family App Note
123 KB
8/2003
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AC182: Axcelerator I/O Selection Guide App Note
362 KB
8/2003
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AC178: Optimal Usage of Global Network Spines in ProASIC
PLUS
Devices App Note
603 KB
7/2003
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AC175: Axcelerator Family PLL and Clock Management App Note
174 KB
6/2003
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AC169: Using A54SX72A and RT54SX72S Quadrant Clocks App Note
582 KB
2/2003
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AC165: Introduction to Actel FPGA Architecture App Note
53 KB
1/2003
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AC163: Axcelerator Carry-Connect Macros App Note
118 KB
1/2003
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AC164: Axcelerator Family Memory Blocks App Note
151 KB
1/2003
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AC160: IEEE Standard 1149.1 (JTAG) in the SX/RTSX/SX-A/eX/RT54SX-S Families App Note
554 KB
10/2002
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AC151: Termination of the Vpp and Mode Pin for RH1020 and RH1280 Devices in a Radiation Environment App Note
48 KB
10/2001
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AC147: Using the BUFD and INVD Delay Macros App Note
76 KB
3/2001
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AC145: Power-Up and Power-Down Behavior of 54SX and RT54SX Devices App Note
77 KB
1/2001
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AC137: Integrating Multiple CPLD Functions in an Actel SX Device App Note
30 KB
3/1999
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AC128: Design Techniques for RadHard FPGAs App Note
62 KB
9/1997
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AC130: Designing State Machines for FPGAs App Note
84 KB
9/1997
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AC122: Optimal Datapath Generation Using ACTgen App Note
121 KB
6/1997
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AC120: Designing FIR Filters with Actel FPGAs App Note
72 KB
6/1997
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AC119: Implementing Three-State and Bidirectional Buses with Multiplexers in Actel FPGAs App Note
57 KB
4/1997
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AC107: HDL Methodology Offers Fast Design Cycle and Vendor Independence App Note
24 KB
4/1996
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AC108: Implementing Multipliers with Actel FPGAs App Note
82 KB
4/1996
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AC110: Synchronous Dividers in Actel FPGAs App Note
37 KB
4/1996
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AC111: Three-Stating Actel Device I/O Pins for Board Level Testing App Note
26 KB
4/1996
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AC117: Using FPGAs for Digital PLL Applications App Note
25 KB
4/1996
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