Axcelerator App Notes

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Axcelerator

AC163: Axcelerator Carry-Connect Macros App Note	121 KB	1/2003	Click on the to rate this document
AC164: Axcelerator Family Memory Blocks App Note	155 KB	1/2003	Click on the to rate this document
AC170: Prototyping RTAX-S Using Axcelerator Devices App Note	134 KB	4/2003	Click on the to rate this document
AC173: Differences Between RTAX-S/SL and Axcelerator App Note	63 KB	5/2003	Click on the to rate this document
AC175: Axcelerator Family PLL and Clock Management App Note	179 KB	6/2003	Click on the to rate this document
AC177: Implementing Multi-Port Memories in Axcelerator Devices App Note Source Code (ZIP, 12 KB, 07/04)	191 KB	7/2003	Click on the to rate this document
AC182: Axcelerator I/O Selection Guide App Note	371 KB	8/2003	Click on the to rate this document
AC183: Using Global Resources in Actel's Axcelerator Family App Note	126 KB	8/2003	Click on the to rate this document
AC184: Migrating from Engineering Silicon to Production Devices for the Axcelerator Family App Note	152 KB	8/2003	Click on the to rate this document
AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note	115 KB	3/2004	Click on the to rate this document
AC204: Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment App Note	82 KB	5/2004	Click on the to rate this document
AC209: Axcelerator Family Footprint Compatibility App Note	45 KB	7/2004	Click on the to rate this document
AC210: Laser Range Finder Using Actel’s Axcelerator FPGA App Note Design File (ZIP, 345 KB, 07/04)	1.5 MB	7/2004	Click on the to rate this document
AC211: 32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA App Note Design File (ZIP, 1.2 MB, 07/04)	657 KB	7/2004	Click on the to rate this document
AC212: Designing a SuperClock with an Axcelerator Device App Note Design File (ZIP, 130 KB, 09/04)	419 KB	9/2004	Click on the to rate this document
AC217: IEEE Standard 1149.1 (JTAG) in the Axcelerator Family App Note	238 KB	2/2005	Click on the to rate this document
AC218: Using Axcelerator RAM as Multipliers App Note	390 KB	2/2005	Click on the to rate this document
AC228: EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller App Note	730 KB	8/2005	Click on the to rate this document
AC249: I/O Features in Axcelerator Family Devices App Note Relative Pin Locations (ZIP, 341 KB, 11/04)	1.2 MB	1/2006	Click on the to rate this document
AC273: Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs App Note – Applies to EDAC Core from Libero IDE v7.1 and Older EDAC Core from Libero IDE v7.1 or Earlier (ZIP, 41KB, 07/04)	263 KB	7/2006	Click on the to rate this document
AC288: Using LVDS for Actel's Axcelerator and RTAX-S/SL Devices App Note	676 KB	10/2006	Click on the to rate this document
AC319: Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs App Note – Applies to EDAC Core from Libero IDE v7.2 and Newer EDAC Core from Libero IDE v7.2 (ZIP, 45 KB, 06/06)	707 KB	2/2008	Click on the to rate this document