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Actel Libero IDE training is a 2-day course offered at Actel's headquarters in Mountain View, CA. The course consists of lectures and hands-on labs using VHDL or Verilog. Each student will learn how to use Actel's Libero IDE to take a design from conception to a functioning Actel FPGA. Each student will be guided through the complete design flow of a simple hierarchical design using the Libero IDE toolset.

Course Objectives:

• Project creation with the Libero IDE
• HDL entry using the Libero IDE HDL Editor
• Understanding and using Actel's SmartGen core generator
• Constraining designs and synthesizing with Synplicity's Synplify
• Testbench generation with SynaptiCAD's WaveFormer Lite
• Simulation using Mentor Graphic's ModelSim Simulator
• Understanding pin assignment with PinEditor
• Floorplanning with ChipPlanner
• Static timing analysis
• Design layout (place-and-route)
• Generation of back-annotated timing files and programming files
• FPGA programming with the FlashPro Lite programmer

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Introduction to VHDL is a 1-day class for the VHDL novice offered at Actel's headquarters in Mountain View, CA. It can be taken standalone or as an optional first day for students enrolling in the Actel Libero IDE training course. The course features a presentation on VHDL and hands-on labs.

Course Objectives:  

• Develop an understanding of the basic VHDL building blocks including entities, architectures, configurations, package declarations, and package bodies
• Write and synthesize simple Register Transfer Level (RTL) VHDL descriptions
• Creating hierarchical VHDL designs
• Creating testbenches and simulate a design

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Advanced VHDL is a 1-day class for engineers who have basic VHDL knowledge. The class begins with a review of basic VHDL concepts. Advanced topics such as procedures, functions, arrays, generate statements, and testbench generation are discussed. Hands-on labs are included.

Course Objectives:

• Review of the basic VHDL concepts.
• Write and synthesize simple Register Transfer Level (RTL) VHDL descriptions using procedures, function calls, and generate statements.
• Writing testbenches and simulating designs.

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset
• Basic understanding of the VHDL language

Suggested Prerequisite:

• Introduction to VHDL

Introduction to Verilog is a 1-day class for the Verilog novice offered at Actel's headquarters in Mountain View, CA. It can be taken standalone or as an optional first day for students enrolling in the Actel Libero IDE training course. The course features a presentation on Verilog constructs and hands-on labs.

Course Objectives:

• Develop an understanding of the basic Verilog building blocks
• Write and synthesize simple Register Transfer Level (RTL) Verilog descriptions
• Create hierarchical Verilog designs

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Advanced Verilog is a 1-day class for engineers who have basic Verilog knowledge. The class begins with a review of basic Verilog concepts with an emphasis on differences from VHDL. Advanced modeling is covered along with the Verilog Programming Language Interface (PLI). Additional topics include test vectors and simulation in Verilog as well as Verilog-2001 enhancements. Hands-on labs are included.

Course Objectives:

• Review of the basic Verilog concepts
• Write and synthesize simple Register Transfer Level (RTL) Verilog descriptions using Verilog 2001 constructs

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset
• Basic understanding of the Verilog language

Suggested Prerequisite:

• Introduction to Verilog

Introduction to Actel Fusion is a 1-day class for engineers who are designing with Actel's Fusion mixed-signal FPGA. This class describes the Actel Fusion architecture, including Fusion Analog blocks, the Fusion bus interface, FlashROM and the software tools for implementing Fusion designs. Hands-on lab exercises include performance analysis and use of the special features available in this family.

Course Objectives:

• Understanding the Actel Fusion architecture details
• Understanding how to use architectural features in the Fusion family

Students should have a basic understanding of the Actel ProASIC3 Flash-based FPGA architecture. If students are unfamiliar with ProASIC3, Actel recommends that they the Designing with ProASIC3 training class.

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Advanced Fusion Design is a 1-day class with additional information on the Introduction to Actel Fusion training class. The course examines the Fusion mixed-signal FPGA architecture in detail, including the NVRAM and Analog block along with the software tools to implement designs. Applications using the Fusion peripherals such as data logging, context switching, and power sequencing are introduced. Additional topics include Fusion soft IP, simulation of analog inputs, synthesis, and layout. Hands-on lab exercises are provided to reinforce the topics presented.

Course Objectives:

• Detailed understanding of the architectural features in the Fusion family
• Understanding of how to configure the Fusion peripherals
• Understanding simulation, synthesis, and layout
• Introduction to Fusion applications

Students should have a basic understanding of the Fusion architecture. If students are unfamiliar with Fusion, Actel recommends that they attend the Introduction to Actel Fusion training class.

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Suggested Prerequisite:

• Introduction to Actel Fusion

Motor Control with Actel Fusion is a 1-day class for engineers who are designing with Actel's Fusion mixed-signal FPGA family. This course describes the basics of motors—DC (brushed and brushless), AC induction motors, stepper motors, and switched-reluctance motors—as well as the control strategies for each type. The course presents a brief overview of Fusion features for motor control and then discusses specific Fusion motor control implementations. Hands-on lab exercises include motor control designs for DC brushless and AC induction motors.

Course Objectives:

• Understanding motor designs and basic motor control strategies
• Understanding the Fusion architecture with an emphasis on features appropriate for motor control
• Functional simulation, synthesis, layout, and timing analysis of motor-control designs in the Actel Fusion family

Note: This is not a training class on the Fusion architecture; for that information, Actel recommends students attend the Introduction to Actel Fusion class.

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

This course will introduce the Actel IGLOO FPGA family as a solution for low power applications. The presentation examines the components of power in an FPGA design, explains how to analyze power consumption using the available Actel analysis tools, introduces the power-friendly features of the IGLOO family, and describes techniques to reduce power consumption in designs. This course includes hands-on labs that demonstrate the use of Actel's power analysis tools and techniques to improve power consumption.

Course Objectives:

• Understanding of different power components in a design
• Understanding of the power-friendly features in the Actel IGLOO FPGA family
• Understanding of power analysis using Actel's SmartPower analysis tool
• Techniques to reduce power consumption in a design

Course Requirements:

• Basic understanding of the ProSIC3 FPGA architecture.
• Knowledge of the Libero IDE toolset and VHDL or Verilog

Designing with ProASIC3 is a 1-day class for engineers who are designing with Actel's ProASIC3-based FPGAs. This class describes the Actel ProASIC3 FPGA architecture, including the logic tile, RAM blocks, clock conditioning circuitry, user FlashROM, and routing resources. This class will also introduce techniques on using the architectural features to improve design performance or area utilization. Hands-on lab exercises include performance analysis and the use of the special features available in this family.

Course Objectives:

• Understanding of the ProASIC3 FPGA family architecture details including:
• Logic tile
• Memory blocks
• Clock conditioning circuitry
• User FlashROM
• Understanding of how to use architectural features in the ProASIC3 family to optimize designs for area or performance
• Migrating designs from ProASIC^PLUS

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

This 1-day course is intended for engineers who are using the Actel SoftConsole Integrated Development Environment (IDE) to develop applications for the 8051, ARM Cortex-M1, or ARM7 microprocessors embedded in an Actel FPGA. Students will learn how to use Actel's SoftConsole to develop and debug software applications. Each student will be guided through the complete design flow of a simple design targeting the 8051, ARM Cortex-M1, or ARM7 processor, including debugging the application on a target board. This course is offered at Actel's headquarters in Mountain View, CA.

Course Objectives:

• SoftConsole Eclipse IDE Overview
• Project creation
• Code development tools
• Source code development and simulation
• Configuring the on-chip debugger
• Debugging applications in a target system

Course Requirements:

• Basic understanding of the 8051, ARM Cortex-M1, or ARM7 architecture
• Familiarity with assembler and C-programming
• Familiarity with the Windows operating system

Introduction to Cortex-M1 is a 1-day class offered at Actel's headquarters in Mountain View, CA. The course introduces the Cortex-M1 architecture, instruction set and bus transactions, as well as information on the Cortex-M1 module. In addition, the students will use Cortex-M1 development tools such as CoreConsole (Cortex-M1/AMBA system development environment) and SoftConsole. Hands-on lab exercises will allow students to create a CortexM1-based system, simulate the design and complete the design flow though layout.

Course Objectives:

• Understanding basic Cortex-M1 architecture and bus transactions
• Understanding the Cortex-M1 module with a focus on the backend interface
• Functional simulation, synthesis, layout, and timing analysis of the Actel CoreMP7 module
• System usage of the Cortex-M1 module

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Introduction to CoreMP7 is a 1-day class offered at Actel's headquarters in Mountain View, CA. The course introduces ARM7 concepts and bus transactions, as well as information on the Actel CoreMP7 module. In addition, the students will use ARM7 software tools such as CoreConsole (ARM7/AMBA system development environment). Hands-on lab exercises will allow students to create a CoreMP7-based system, simulate the design and complete the design flow though layout.

Course Objectives:

• Understanding basic ARM7 concepts and bus transactions
• Understanding the Actel CoreMP7 module with a focus on the back-end interface
• Functional simulation, synthesis, layout, and timing analysis of the Actel CoreMP7 module
• System usage of the CoreMP7 module

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Introduction to Core8051 is a 1-day class offered at Actel's headquarters in Mountain View, CA. The course introduces the 8051 architecture and instruction set. In addition, the course provides architectural information on the two Actel versions of the 8051: Core8051 (high-performance, standalone version) and Core8051s (highly-configurable version with an AMBA APB interface). The students will be introduced to Core8051s development tools such as CoreConsole (Core8051s/AMBA system development environment) and SoftConsole. Hands-on lab exercises will allow students to create a Core8051s-based system in CoreConsole, simulate the design, and complete the design flow though layout.

Course Objectives:

• Understanding basic 8051 architecture and instruction set
• Understanding the Actel Core8051 and Core8051s modules with a focus on the Core8051s AMBA APB backend interface
• Functional simulation, synthesis, layout, and timing analysis of the Actel Core8051s module
• System usage of the Core8051s module

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Introduction to CoreABC is a 1-day class offered at Actel's headquarters in Mountain View, CA. The course introduces the Actel CoreABC processor architecture and instruction set. In addition, the course will introduce CoreABC development tools such as CoreConsole and simulation techniques. Hands-on lab exercises allow students to create a system using CoreABC.

Course Objectives:

• Understanding basic CoreABC architecture and instruction set
• Functional simulation, synthesis, layout, and timing analysis of the Actel CoreABC module
• Building a CoreABC system

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Introduction to CorePCIF is a 1-day course offered at Actel's headquarters in Mountain View, CA. The course consists of presentation of PCI concepts and bus transactions, an introduction to the Actel CorePCIF module (with FIFO backend) and hands-on labs.

Course Objectives:

• Understanding of basic PCI concepts and bus transactions
• Understanding of the Actel CorePCIF module with a focus on how the back-end interface works
• Functional simulation, synthesis, layout, and timing analysis of the Actel CorePCIF module

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Advanced CorePCIF is a 1-day course that builds on the Introduction to CorePCIF course and is intended for customers who have purchased the Actel CorePCIF (with FIFO backend) module. The course examines the Actel CorePCIF module architecture in detail and describes synthesis and layout of the cores. Students will look at strategies for area and timing optimization as well as the CorePCIF testbenches. Hands-on lab exercises are provided in simulation, timing optimization, and testbench modification.

Course Objectives:

• Understanding of the Actel CorePCIF (with FIFO back-end) module architecture
• Understanding functional simulation, synthesis, layout, and timing analysis of the CorePCIF module.
• Timing and area optimization of the CorePCIF module.
• Modification of the CorePCIF testbench.

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Suggested Prerequisite:

• Introduction to CorePCIF

Introduction to PCI is a 1-day course offered at Actel's headquarters in Mountain View, CA. The course consists of a presentation on PCI concepts and bus transactions, an introduction to the Actel CorePCI module, and hands-on labs.

Course Objectives:

• Understanding of basic PCI concepts and bus transactions
• Understanding of the Actel CorePCI module with a focus on how the back-end interface works
• Functional simulation, synthesis, layout, and timing analysis of the Actel CorePCI module

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset

Advanced PCI is a 1-day course that builds on the Introduction to PCI course and is intended for customers who have purchased the Actel CorePCI module. The course examines the Actel CorePCI module architecture in detail and describes synthesis and layout of the cores. Students will look at strategies for area and timing optimization as well as the CorePCI testbenches. Hands-on lab exercises are provided in simulation, timing optimization, and testbench modification.

Course Objectives:

• Understanding of the Actel CorePCI architecture
• Understanding functional simulation, synthesis, layout, and timing analysis of the CorePCI module
• Timing and area optimization of the CorePCI module
• Modification of the CorePCI testbench

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset
• Students must have purchased the Actel CorePCI module to attend.

Suggested Prerequisite:

• Introduction to CorePCI

High Speed Antifuse Design is a 1-day class for designers who are using Actel's Axcelerator and RTAX-S FPGAs. The course begins with a review of the antifuse architecture and introduces techniques to improve performance and area utilization. Hands-on labs are included to reinforce the lecture material.

Course Objectives:

• Review of the Actel antifuse FPGA architecture
• Ability to identify the source of timing problems
• Techniques to achieve timing closure or improve area utilization

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset
• Basic understanding of the Actel antifuse FPGA architecture

Suggested Prerequisite:

• Designing with Axcelerator

Designing with RTAX-S is a 1-day course that introduces the antifuse-based, HiRel RTAX-S family. This class describes the specific feature  and architectural differences between the Actel Axcelerator FPGA family and the RTAX-S family such as the EDAC RAM and local clocks. Techniques for improving design performance—both area and timing are also introduced. Hands-on lab exercises include performance analysis and use of the special features available in this family.

Students should be familiar with the Actel Axcelerator FPGA architecture or attend the Designing with Axcelerator training class.

Course Objectives:

• Understanding of the RTAX-S FPGA family architecture details including logic modules, Memory Blocks, Clock Conditioning Circuitry and I/Os
• Understanding of how to use architectural features in the Axcelerator family to optimize designs for area or performance
• Understanding of performance analysis of special architectural features

Course Requirements:

• Experience with PCs, Windows operating system, and Actel Libero IDE toolset