Reducing the Cost of Performance
Actel SX-A devices can match the speed and performance
of an ASIC. SX-A devices can be used to generate system-wide savings by integrating
multiple functions into a low cost, single-chip solution. Providing a combination
of performance, security, and low power, SX-A decreases the premium for performance
while providing a solution highly secure from reverse engineering.
- 12,000 to 108,000 usable system gates
- 350 MHz internal clock frequency
- 66 MHz, 64-bit 3.3 V / 5.0 V PCI performance (supporting Target, Master
and Master/Target)
- 2.5 V, 3.3 V, and 5.0 V mixed-voltage support
- 100% resource utilization with 100% pin locking
- Available in military and automotive temperature grades
SX devices have been classified as a "legacy" device. For more information,
visit the Legacy FPGAs page.
| Device |
A54SX08A |
A54SX16A |
A54SX32A |
A54SX72A |
| Capacity |
| Typical Gates |
8,000 |
16,000 |
32,000 |
72,000 |
| System Gates |
12,000 |
24,000 |
48,000 |
108,000 |
| Logic Modules |
768 |
1,452 |
2,880 |
6,036 |
| Combinatorial Cells |
512 |
924 |
1,800 |
4,024 |
| Dedicated Flip-Flops |
256 |
528 |
1,080 |
2,012 |
| Maximum Flip-Flops |
512 * |
990 |
1,980 |
4,024 |
| Maximum User I/Os |
130 |
180 |
249 |
360 |
| Global Clocks |
3 |
3 |
3 |
3 |
| Quadrant Clocks |
0 |
0 |
0 |
4 |
| Boundary Scan Testing |
Yes |
Yes |
Yes |
Yes |
| JTAG |
|
|
|
|
| 3.3 V / 5 V PCI |
Yes |
Yes |
Yes |
Yes |
| Clock-to-Out |
|
|
|
|
| Input Set-Up (External) |
0 ns |
0 ns |
0 ns |
0 ns |
| Speed Grades |
-F, Std.,
-1, -2 |
-F, Std.,
-1, -2 |
-F, Std.,
-1, -2 |
-F, Std.,
-1, -2 |
| Temperature Grades |
C, I, A, M |
C, I, A, M |
C, I, A, M, B |
C, I, A, M, B |
| Package (by
pin count) |
| PQFP |
208 |
208 |
208 |
208 |
| TQFP |
100, 144 |
100, 144 |
100, 144, 176 |
|
| PBGA |
|
|
329 |
|
| FBGA |
144 |
144, 256 |
144, 256, 484 |
256, 484 |
| CQFP |
|
|
84, 208, 256 |
208, 256 |
Note: *
A maximum of 512 registers is possible if all 512 C-cells are used to build
an additional 256 registers.
The
SX-A family of FPGAs is fully supported by Actel Libero IDE, a design management environment that guides the user through the
FPGA design flow and provides seamless design tool integration as well
as project, data file, and log file management. Libero IDE enables users
to integrate both schematic and HDL synthesis into a single flow and verify
the entire design in a single environment. The Actel Designer toolset
is included for backend product implementation and programming file generation.
CorePCI,
Core1553BRT, and Core1553BBC evaluation boards are available with a
socketed A54SX32A-BG329 device. Each PCI card is interfaced to a shared
synchronous external SSRAM memory and provides an RS-232 port and Silicon
Explorer connector.
The antifuse architecture is one-time programmable (OTP) by design and
devices are not in-system programmable. Device programming is supported
through the Silicon
Sculptor 3 series of programmers, which include a high-speed USB 2.0
port. Up to twelve Silicon Sculptor 3 programmers may be connected to a
single PC. Silicon Sculptor 3 also provides extensive hardware self-testing
along with integrity test. For real-time debugging, Silicon
Explorer II can be used to sample the built-in probe signals of the
antifuse architecture.
Search for
SX-A IP Cores.
| Technology Solutions |
 |
Does not require additional configuration nonvolatile memory in order
to load the device configuration data at every system power-up, which
reduces cost and increases security and system reliability. |
|
Greatly simplifies system design, making the device available to
perform critical system setup tasks and reduce bill-of-materials costs
and PCB area. » More
|
|
Antifuse programmable technology is inherently protected against
reverse engineering and unauthorized duplication. » More
|
|
Antifuse configuration elements cannot be altered by high-energy
atmospheric neutrons and are therefore suitable for high reliability
applications at ground level and at aviation altitudes. » More
|
