Reset Management in High Availability Systems is often overlooked by providers of power supply sequencing ASSPs. Reset Management and power supply sequencing are intertwined. As power supplies power up, the load that is being supplied power needs to be released from reset. In fact, identical devices from the same manufacturer often exhibit slightly different reset requirements. That is to say, one device may have to be released from reset 10ms later than an identical device. In addition, during system level debug users would like control over these resets as they often have to restart a chip during the debug cycle.
The I2C bus has been a staple of the command and control plane in the communications market for decades. From GPIO expanders to ADC converters, to temperature sensors, you will typically find many I2C busses in any given communications systems. However, today’s modern high end communications processors are sporting multi-lane PCIe root complexes. The trend in the HA market is to aggregate I2C traffic from multiple sources into a single PCIe lane back to the system processor. Having multiple I2C master devices aggregate I2C traffic onto a high speed PCIe bus keeps I2C bus lengths short, improves turnaround time on sampling I2C devices in system, which can, in turn, alert the end user to a potential problem sooner rather than later.
Where there are many supplies, there is heat. Applying the right amount of cooling at the right time requires a reliable fan controller. Users can operate fans in basically one of two modes, Open loop, or closed loop. Closed loop control offers some distinct advantages:
- Lowering power by only turning a fan as fast as you need which also lowers ambient noise
- Predicting fan failure
- Measuring commanded RPM versus actual RPM can be a leading indicator of bearing failure.
Something as simple as controlling a fan, if not done reliably, can lead to higher operating costs.
Another approach for reliable fan control is to embed CoreI2C with CorePWM into a low gate / pin count A3P or Igloo device for a single fan controller point solution. The loop can be closed in the Host MPU by reading tachometer position from CorePWM via the I2C bus.
Today’s high end communications and compute processors typically have a boot rom on chip that allows end users to choose various boot interfaces and fetch the application image for loading into high performance DDR memory. This primary boot function is typically not secure. To boot today’s high end processors securely. Users can use SmartFusion or SmartFusion2 as a root of trust. The on-chip eNVM can contain the secondary bootloader needed to complete the copy of the executable image from flash to DDR memory. In addition SmartFusion or SmartFusion2 allows end users to encrypt the application image in external Flash reducing the possibility of cloned systems. By programming SmartFusion or SmartFusion2 with the secondary bootloader the user can ensure they boot from a secure and reliable source, thereby allowing the system to power-up in a secure and reliable manner.
In High Availability systems enhancements to services, patches, and new customer requirements all drive the requirement for a remote update capability. Being able to update remotely is only part of the problem. It has to be done in a secure and bullet proof fashion. SmartFusion and SmartFusion2 incorporate facilities that manage the programming of the device from an external SPI flash. The customer application can update this external SPI flash with a new image, and then start a new programming operation.
In SmartFusion2, there is an option to allow a secondary SPI flash that can only read from. There is no way to write to this SPI flash from SmartFusion2. Users can enable the Write Protect pin on these flash devices for a further level of reliability. SmartFusion2 will reprogram from this flash device when the FLASH_GOLDEN pin is asserted on power-up.
Instant - On
System Management solutions are the 1st to power-up from auxiliary power. SmartFusion and SmartFusion2’s flash based FPGA fabric doesn’t need to load on power up from an external memory. It powers up like an ASIC. This leads to quicker system turn on time but also has some subtle side benefits. Your IP is not exposed during the boot process and inrush currents are minimized as compared to SRAM based alternatives which lower your operating costs.
Mixed Signal Power Manager (MPM)
Microsemi has developed robust High Availability (HA) system solutions in line with the needs of customers over the last three generations of FPGA solutions. IGLOO® low power FPGAs provide all of the features for a low complexity HA system, while the addition of analog blocks in Microsemi Fusion® mixed signal FPGAs provides on-chip monitoring of temperature and the ability to margin supplies in design and production testing. The highly integrated SmartFusion SoC products add an industry standard cortex-M3 processor for controlling PMBus power supplies and SmartFusion2 brings higher levels of performance, security and reliability along with high speed communications interfaces to your system management solution.