Lower system power consumption is a requirement for more applications than ever due to the dramatic increase in power-conscious applications and tighter power budgets. Today, FPGA technology is increasing in usage in low-power applications, which makes achieving lower system power an increasingly important challenge. FPGAs have been adopted widely in recent years due to advanced technology that lowered the unit price, but the price reductions have come at the cost of higher power due to higher transistor leakage. The various FPGA technologies have significantly different power profiles, and these differences can have a profound impact on the overall system design and power budget. Actel's ultra-low-power flash FPGAs lead the industry with lowest power (as low as 2 µW), selection of power modes, small form factor packages (as small as 3x3 mm), and low cost (as little as $0.49).

Total System Power

There are five basic power components that need to be examined when evaluating the power consumption of different FPGA technologies:

1. Static power
2. Dynamic power
3. Power-up (or inrush power)
4. Configuration power
5. Sleep (low-power) mode power

The total system power is a combination of all five of the power components over time.

The following comparison charts show the power-up power profile (on the left) and the operation power profiles (on the right) between SRAM-based FPGAs and flash/antifuse nonvolatile FPGAs.

Power Profile and Consumption

Using Actel IGLOO devices can provide ten times the battery life of their nearest low-power competitor while Actel IGLOO PLUS devices offer 16X power per I/O savings compared with its nearest competitors. This is due to the overall superior power profile and lower power consumption in all five stages of system operation.

The following charts show the battery life per device and power per I/O savings, and are based on vendor software power analysis tools.

Using IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3, ProASIC3 nano, and ProASIC3L low-power flash FPGAs and Fusion mixed-signal FPGA can reduce power dissipation to as low as 2 µW by using the low-power modes available on these devices.

IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3, ProASIC3L, and ProASIC3 nano Devices

Fusion Devices

A Power-Driven Layout (PDL) option in Actel's Libero IDE and Designer software tools drive placement of the design based on an imported simulation Value Change Dump (VCD) file, or SmartPower's design analysis data. With little to no impact on timing of the design, the PDL flow guides placement of the physical layout of IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3, ProASIC3 nano, ProASIC3L, and Fusion designs to achieve the lowest possible dynamic power consumption for power-conscious applications. For IGLOO designs, an average of 13% power reduction has been obtained, with some specific designs realizing as much as 30% dynamic power reduction.

Power Calculators

• Use these family specific spreadsheet-based tools to obtain a pre-netlist power estimation of your proposed design.

SmartPower

• SmartPower is part of the Libero IDE FPGA design/development tool suite and is used to obtain detailed power analysis of your design after the netlist has been compiled and place-and-route has been run.