Algorithm Design
Starting with a concept, a DSP architect translates ideas into a design
in the MATLAB and Simulink environment. DSP blocks supplied by the FPGA
or the EDA tool vendors are used at this stage. For instance, targeting
the Actel FPGA device, the architect or designer uses blocksets supplied
by Synphony Model Compiler AE and/or Actel IP.
The figure below shows an example of how to create a design in Simulink
and use the Filter Design Analysis tool from MATLAB. Start the design
capture by dragging in the desired blocks and connecting them up to realize
the desired function. Once the design capture is done, the Filter tool
provides a convenient facility for analyzing the functional behavior
of the filter.
Conversion to Fixed Point
Simulink provides an environment for simulating the design and analyzing
its behavior using floating point and fixed-point accuracies. Simulation
can be performed using the built-in stimuli and scope block sets in Simulink.
Floating point format provides a baseline performance of the algorithm
that helps in the analysis of the fixed-point behavior of the design.
As shown in the figure below, the fixed-point tool in Synphony Model Compiler AE
helps to automatically change the accuracy of the data. The effects of
the tradeoffs can be easily viewed in the scope.
High Level Synthesis Optimization and RTL Generation
The DSP design can be synthesized into architecturally-optimized RTL by using Synphony Model Compiler AE, which is a high level synthesis (HLS) tool that performs architectural optimizations from the Simulink specification. These HLS optimizations allow designers to capture the behavior needed for their algorithm without worrying about the specific implementation in hardware. Synphony Model Compiler AE performs transformations and optimizations of the DSP Simulink design based on the Actel target device and then generates the RTL.
Synphony Model Compiler AE Optimization Strategies
- Folding: This optimization strategy helps in reducing the area utilization by reusing the same area hardware components (such as multipliers) for multiple streams of data. This results in a very compact design. This optimization is a tradeoff between the area utilization of the hardware and the higher clock rate required to maintain similar data rates.
- Retiming: Retiming optimization is similar to the register balancing optimization done at the RTL Synthesis level; in this case, though, the optimization is done at the system architecture level.
- Multi-Channelization: Once a algorithm has been developed and verified in Simulink, the design can then be replicated over multiple channels. This optimization replicates the design and then automatically applies optimizations which synthesizes the time-domain multiplexer logic required for better area.
More Synphony Model Compiler AE Features:
- Rapid algorithm design and simulation in Simulink
- Easy floating and fixed-point conversion and analysis
- Fully integrated fixed-point blockset of DSP functions
- User-customizable IP blockset
- Automatic generation of code and testbench RTL
- New system-level optimizations for improved performance and area
- VHDL and Verilog language support
- Co-simulation with ModelSim
For further information on Synphony Model Compiler, refer to the Synopsys website. For use with Actel devices download Synphony Model Compiler AE from the Actel website
Physical Implementation
The figure below shows the FPGA implementation environment where the
RTL design generated from Synphony Model Compiler AE is synthesized, simulated (optional),
and mapped to the FPGA device. There are several tools involved in this
process; the design flow has been made easy with the flowchart shown
in the tool. You push the relevant buttons in the flow to complete the
tasks.
