Overall DSP Design Flow
The following block diagram shows the DSP design flow. The RTL for DSP
design and the top-level system design flow into the Libero IDE that
conveniently manages the synthesis, simulation, place-and-route, and
programming flow.
DSP Design FLow Example
Algorithm
Design -> Conversion to Fixed-Point -> RTL Generation -> Libero
IDE
Algorithm Design
Starting with a concept, a DSP architect translates ideas into a design
in the Matlab and Simulink environment. DSP blocks supplied by the FPGA
or the EDA tool vendors are used at this stage. For instance, targeting
the Actel FPGA device, the architect or designer uses blocksets supplied
by Synplify DSP AE and/or Actel IP.
The figure below shows an example of how to create a design in Simulink
and use the Filter Design Analysis tool from Matlab. Start the design
capture by dragging in the desired blocks and connecting them up to realize
the desired function. Once the design capture is done, the Filter tool
provides a convenient facility for analyzing the functional behavior
of the filter.
Conversion to Fixed Point
Simulink provides an environment for simulating the design and analyzing
its behavior using floating point and fixed-point accuracies. Simulation
can be performed using the built-in stimuli and scope block sets in Simulink.
Floating point format provides a baseline performance of the algorithm
that helps in the analysis of the fixed-point behavior of the design.
As shown in the figure below, the fixed-point tool in Synplify DSP AE
helps to automatically change the accuracy of the data. The effects of
the tradeoffs can be easily viewed in the scope.
RTL Design Generation
The DSP design can be converted into RTL by using Synplify DSP AE, which
is a true DSP synthesis tool that performs high-level DSP optimizations
from a Simulink specification. These special DSP optimizations allow
designers to capture the behavior needed for their DSP algorithm without
worrying about the specific implementation in hardware. Synplify DSP
AE automatically creates the RTL for DSP design within the Simulink environment.
Synplify DSP AE Optimization Strategies
- Folding: This optimization strategy helps in reducing
the area utilization by reusing the same area hardware components (such
as multipliers) for multiple streams of data. This results in a very
compact design. This optimization is a tradeoff between the area utilization
of the hardware and the higher clock rate required to maintain similar
data rates.
- Retiming: Retiming optimization is similar to the
register balancing optimization done at the RTL Synthesis level; in
this case, though, the optimization is done at the system level.
- Multi-Channelization: Once a DSP algorithm has been
developed and verified in Simulink, the design can then be replicated
over multiple channels. This optimization automatically creates the
multiplexer logic required for passing the input data stream over the
corresponding channels.
More Synplify DSP AE Features:
- Rapid algorithm design and simulation in Simulink
- Easy floating and fixed-point conversion and analysis
- Fully integrated fixed-point blockset of DSP functions
- User-customizable IP blockset
- Automatic generation of code and testbench RTL
- New system-level optimizations for improved performance and area
- VHDL and Verilog language support
- Co-simulation with ModelSim
Physical Implementation
The figure below shows the FPGA implementation environment where the
RTL design generated from Synplify DSP AE is synthesized, simulated (optional),
and mapped to the FPGA device. There are several tools involved in this
process; the design flow has been made easy with the flowchart shown
in the tool. You push the relevant buttons in the flow to complete the
tasks.
