CoVer™ is a Windows®-based hardware/software co-verification
solution offered by Aldec. It is targeted for Actel's CoreMP7 soft
ARM7 core, allowing both hardware and software engineers to debug designs
targeted for CoreMP7.
This solution benefits both software and hardware engineers, allowing them to
debug designs targeting real-on-chip processor, instead of using BFM (Bus Functional Model).
Use of co-verification can offer faster time to market and optimized design cycles. Here Aldec's patented Smart
Clock technology is used to enable automatic switching between an HDL simulator
generated clock (software) and an oscillator clock on board (hardware), enabling
customers to take advantage of both on-chip-performance and debugger stepping.
The design flow involves software and hardware. Software such as CoreConsole, SoftConsole, Libero
IDE, and ActiveHDL are provided by both Actel and Aldec. They are
used to construct an overall system including processor, compile C code,
manage the overall project, and simulate designs. Hardware consists of a reusable
FPGA prototyping board, provided by Aldec. This board is used to load
the customer design and capture the interface and internal signals for
verification and validation.
- Real hardware processor instead of Bus Functional Model (BFM)
- Reduction of test bench development time
- Parallel debugging of HW/SW units
Package
The package consists of hardware/software from both Aldec and Actel:
- Aldec's Active-HDL mixed-language simulator
- Aldec's CoVer_ActelMP7 software
- Aldec's FPGA prototyping board with CoreMP7 device
- Actel's system-level development tool (CoreConsole)
- Actel's software development and software debugger (SoftConsole)
- Actel's Libero Gold IDE
