Availability, Reliability, and Maintainability have been cornerstones in the communications and computing market for decades. Critical infrastructure must work all the time. The business of everything depends on it. As the connectivity of the world increases a fourth element (Securability) to these core concepts has come to the forefront of modern communications and computing systems. Securability is a part of, and, integral to Availability, Reliability and Maintainability. Your system must be secure in its design, manufacture, deployment, operation, and maintenance. ARMS all must work together to provide resilient and consistent services to end users. Microsemi SoC FPGA's have unique features that address Availability, Reliability, Maintainability and Securability.
- Most reliable SoC FPGA
- SEU Immune Zero FIT Flash FPGA Configuration Cells
- Built-In Self Test (non-volatile memory digest)
- SEU Protected memories
- World's most secure Soc FPGA
- Root of Trust
- Differential Power Analysis (DPA) Hardened
- Anti-Tamper Detectors
- Security Accelerators
- Supply Chain Assurance X.509 Digital Certificate
- Update your system remotely and securely over high speed communications links:
- PCI Express Gen1 and Gen 2 Endpoints
- Triple Speed 10/100/1000 Ethernet
- HS USB 2.0 OTG
- Lowest power SoC FPGA (M2S050T)
- 1 mW in flash-freeze mode
- 10 mW static power during operation
Power Supply Sequencing
As systems and SoC's become more complicated so do the power supply sequencing requirements. A flexible and reliable power supply sequencing solution can make this complicated task easier to solve. Microsemi's Micro Power Manager (MPM) can make a complex problem easier to manage. Click here to learn more about MPM. http://www.microsemi.com/soc/products/solutions/systemmgt/default.aspx
Similar to power supply sequencing, Reset sequencing and control is a necessary function during board bring up and during system level integration. Control of reset lines should not be left to a microcontroller that doesn't error correct the internal memories nor to SRAM FPGA's that are prone to configuration memory upsets. You do not want a reset signal to assert at the wrong time.
Bridging - PCIe to I2C bridging
I2C devices are used extensively in today's communications systems. They're easy to use, they offer point solutions, and sometimes are the only solution available. Multi- gigahertz processors weren't designed to manage these low level components. You don't want to continuously interrupt these processors when events occur over the I2C bus. A better solution is to offload the management of these tasks to a real time Soc FPGA. Smartfusion2 is optimally suited to manage all of these low level devices and aggregate the I2C bandwidth to the host processor over a single PCIe Gen1 or Gen2 lane.
Today's high end communications and compute processors typically have a boot rom on chip that allows end users to choose various boot interfaces and fetch the application image for loading into high performance DDR memory. This primary boot function is typically not secure. To boot today's high end processors securely. Users can use SmartFusion or SmartFusion2 as a root of trust. The on-chip eNVM can contain the secondary bootloader needed to complete the copy of the executable image from flash to DDR memory. In addition SmartFusion or SmartFusion2 allows end users to encrypt the application image in external Flash reducing the possibility of cloned systems. By programming SmartFusion or SmartFusion2 with the secondary bootloader the user can ensure they boot from a secure and reliable source, thereby allowing the system to power-up in a secure and reliable manner.
Closed loop Fan Control
Closed loop fan control is superior to open loop fan control. Benefits include:
- Lower ambient noise - apply only the amount of cooling needed
- Redundant fan switchover capability
- The ability to predict fan failure.
Microsemi's CorePWM IP is a low-cost tachometer solution with up to 16 separate digital inputs that allow users to implement closed loop cooling systems. The block diagram below illustrates a dual channel Fan controller as part of an overall system management function in SmartFusion2
Another approach for reliable fan control is to embed CoreI2C with CorePWM into a low gate / pin count A3P or Igloo device for a single fan controller point solution. The loop can be closed in the Host MPU by reading tachometer position from CorePWM via the I2C bus.