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Merging Graphical Design Entry with HDL Abstraction
Replacing CoreConsole, SmartDesign is the next-generation "design creation" tool that greatly simplifies construction of simple and complex designs. Conventional design approaches use schematic and HDL code generation. While designing at this level is a well seasoned design practice used by many, what has been missing is a capability to build and visualize such designs as a higher level modular system or subsystem, and automatically abstract the work into a single functional HDL file that is synthesis ready.
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SmartDesign is Actel's advanced graphical block-level platform for creating simple and complex designs, including processor and bus-based System-On-Chip (SoC) designs. SmartDesign provides a powerful common visual block-level platform for instantiation and connection of Actel DirectCores and SmartGen cores, user-created Designer blocks, DSP modules, IP, and custom HDL functions and glue logic, or third party generated cores and solutions. The final result is a design rule checked and automatically abstracted synthesis-ready HDL file. A "SmartDesign" can be the entire FPGA design or a sub-system as part of a larger SmartDesign.
SmartDesign Flow
Key Features
- Visual block-based design creation tool
- Assemble and connect DirectCores, SmartGen Cores, user-generated IP, custom/glue-logic HDL modules
- All construction performed within a single "canvas" view
- All ports exposed on the canvas, available for connection
- Automatic connections to compatible peripherals and busses
- Point-and-click manual connections
- Guidance to compatible interfaces and required peripherals
- Dynamic error check, continuous file audit
- Automatic generation of test bench for clock and resets
- Bus Functional Model (BFM) generation for processor designs
- Datasheet report
- View the entire SmartDesign as a system, with all interconnects
- Automatic abstraction to synthesis-ready HDL: Verilog or VHDL
- Efficient construction of complex processor, bus-based, Fusion mixed-signal FPGA, and simple designs
- Complete FPGA SoC, FPGA subsystem, or embedded SmartDesign-in-SmartDesign
SmartDesign makes use of Actel's extensive pre-defined catalog library of DirectCores or SmartGen cores that are already proven functional blocks, allowing easy placement on a white-board-like "canvas" where they can be arranged as a system block diagram. All connections to the blocks and device pins are made on a "Canvas" where you can visualize the complete functionality of the design as it evolves. The core of interest is simply selected from the catalog and dragged onto the canvas, a configuration dialog is opened, and when completed the core is visible on the canvas as a block instance complete with all ports waiting for connection. Connections are easily made either automatically depending on the interface, or manually by point and click from one port to another. Connections and interconnecting nets and net names can be viewed or not viewed as needed.
With SmartDesign, you no longer have to create a schematic from low level gates and registers, nor do you have to build the design ground up by creating HDL code. SmartDesign does however also accommodate your own HDL modules or Designer blocks previously created in Libero IDE.
To produce a pleasing view of the block system the SmartDesign canvas allows you to move and re-arrange blocks and busses without losing connections, and an "auto-arrange" feature attempts to present a simplified layout. The contents of the canvas can be easily printed for hard-copy archive.
SmartDesign and Core Catalog
A design rule check ensures that all ports are connected properly. Any unconnected ports will be displayed in a "Connectivity Checker" grid, providing a straight forward dialog and methodology to make any final connections.
Connectivity Checker Grid
A schematic view provides a traditional HDL/schematic view of the evolving SmartDesign, where all blocks, ports, buses, and pins are shown.
Schematic View
After visually verifying on the canvas, connections grid, or schematic views, with a simple click SmartDesign runs a design rule check and converts the system into synthesis ready HDL.
SmartDesign is part of the Libero IDE toolset and is available in all Libero IDE editions. No special license is required for SmartDesign. Check DirectCores for core-specific license information.
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For more documentation, refer to the Design Entry Application Notes.
Additional Design Development Tools
