Merging Graphical Design Entry with HDL Abstraction

SmartDesign is the next-generation design creation tool that greatly simplifies construction of simple and complex designs. Conventional design approaches use schematic and HDL code generation. While designing at this level is a well-seasoned design practice used by many, what has been missing is a capability to build and visualize such designs as a higher level modular system or subsystem, and then automatically abstract the work into a single functional HDL file that is synthesis ready.

SmartDesign is Microsemi's advanced graphical block-level platform for creating simple and complex designs, including processor-based and bus-based System-On-Chip(SoC) designs. SmartDesign provides a powerful common visual block-level platform for instantiation and connection of Microsemi IP Cores, common cores, DSP modules, IP, and custom HDL functions and glue logic, or third-party-generated cores and solutions. The final result is a design-rule-checked and automatically abstracted synthesis-ready HDL file. A design using SmartDesign can be the entire FPGA design or a component subsystem of a larger design.

SmartDesign Flow

Key Features

• Visual block-based design creation tool
• Assemble and connect Microsemi IP, user-generated IP, custom/glue-logic HDL modules
• All construction performed within a single canvas view
• All ports exposed on the canvas, available for connection
• Automatic connections to compatible peripherals and busses
• Point-and-click manual connections
• Guidance to compatible interfaces and required peripherals
• Dynamic error check, continuous file audit
• Automatic generation of test bench for clock and resets
• Bus functional model (BFM) generation for processor designs
• Datasheet report
• View the entire SmartDesign as a system, with all interconnects
• Automatic abstraction to synthesis-ready HDL: Verilog or VHDL
• Efficient construction of complex or simple designs, including bus-based designs with processor and SmartFusion or Fusion mixed signal FPGAs
• Complete FPGA SoC, FPGA subsystem, or embedded SmartDesign-in-SmartDesign
• Converts CoreConsole projects to SmartDesign projects (applicable to v8.5 and later versions)
• Now supported in Designer and Libero Standalone (SA) licenses (applicable to v8.5 and later versions)

SmartDesign makes use of Microsemi's extensive pre-defined catalog library of IP and common cores that are proven functional blocks, allowing easy placement on a white-board-like canvas where they can be arranged as a system block diagram. All connections to the blocks and device pins are made on the canvas, where you can visualize the complete functionality of the design as it evolves. The selected core can be dragged from the Catalog window onto the canvas. A dialog opens to assist with configuration, after which the core is visible on the canvas as a block instance, complete with all ports waiting for connection. Connections are easily made either automatically, depending on the interface, or manually by point-and-click from one port to another. Connections and interconnecting nets and net names can be viewed or hidden as needed.

With SmartDesign, you no longer have to create a schematic from low-level gates and registers or build the design ground up by creating HDL code. SmartDesign does, however, also accommodate your own HDL modules or Designer blocks previously created in Libero IDE.

To produce a pleasing view of the block system, the SmartDesign canvas allows you to move and re-arrange blocks and busses without losing connections, and an auto-arrange feature attempts to present a simplified layout. The contents of the canvas can be easily printed for hard-copy archive.

SmartDesign Canvas and Core Catalog

SmartFusion designs start with the configuration of various peripherals within the SmartDesign microcontroller subsystem (MSS) unique to SmartFusion. Various peripherals within the MSS, such as the ARM® Cortex™-M3, analog compute engine (ACE), embedded nonvolatile memory (eNVM), Ethernet MAC, timer, UART, and SPI, are configurable in order to customize the MSS to your specific system needs. The MSS operates standalone without any dependencies on other logic within the SmartFusion device; however, designs that require functionality beyond a standalone MSS are handled by using SmartDesign to add user logic in the SmartFusion FPGA fabric.

The FPGA fabric can be populated with Microsemi IP, common cores, or user custom logic using SmartDesign. Designers can add functionality to support the MSS peripherals to build complete embedded SoC designs. Users configure the necessary blocks within the MSS including the fabric interface and proceed to add the appropriate AHP or APB bus interface and other catalog IP or HDL functions to complete the entire design. Once the SmartFusion FPGA fabric is populated in the conventional SmartDesign flow, the entire SmartDesign is automatically design rule checked, abstracted to synthesis-ready HDL, and placed as a component into the design hierarchy. SmartFusion MSS designs not requiring additional logic or use of the FPGA array fabric need only be aligned with appropriate MSS firmware and configured with available software IDEs, such as Microsemi's SoftConsole Eclipse-based IDE, Keil™ Microcontroller Design Kit (MDK), or IAR Embedded Workbench®.

MSS ACE Configurator Example and Connection to FPGA Array Fabric

SmartDesign for SmartFusion also includes the capability to manage I/O attributes and select firmware. I/O settings such as I/O standards, directions, slew rates, output loads, and pin assignments can be viewed and modified. For the various IP cores that are used in the MSS and FPGA fabric, SmartDesign's Firmware tab presents a list of firmware drivers required to support each of the respective IP instantiations, thus removing any guesswork by the designer. The I/O editor and firmware generation features are unique to SmartFusion design projects.

SmartDesign I/O Attributes and Firmware Selection

To learn more about the firmware MSS drivers and configurators, read the Microsemi SmartFusion MSS Configurators and Drivers User's Guides.

SmartDesign is part of the Libero IDE toolset and is available in all Libero IDE editions. No special license is required for SmartDesign. Check Microsemi IP Cores for core-specific license information.

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