SmartTime Timing Constraints and Timing Analysis
SmartTime is a gate-level static timing analysis tool for the
Fusion,
IGLOO,
ProASIC3L (excluding M1 variants),
ProASIC3,
ProASICPLUS,
ProASIC,
Axcelerator,
SX-A,
and
eX families.
With SmartTime, you can perform complete timing analysis of your design
to ensure that you meet all timing constraints and that your design
operates at the desired speed with the right amount of margin across
all operating conditions.
Timing Constraints
SmartTime supports a range of timing constraints to provide useful
analysis and efficient timing-driven layout. Most constraints that
can be generated by Synthesis tools, such as clocks, input arrival
times, and output required times, are automatically passed to SmartTime
in an SDC file. You can edit these constraints in the SmartTime Constraints
Editor. An easy to use wizard for creating timing constraints guides
you to set up the specific constraints for your design. Page-by-page
dialogs with graphical aids assist you to understand and set constraints
for overall/explicit clocks, I/O requirements or specific clock delays
with minimum/maximum input and output delays, generated clocks, and
input and output pin clock requirements. A summary dialog allows you
to confirm all selections made.
SmartTime enables you set up, save, and test timing constraint "scenarios" to
help you better understand the timing capability and performance of
your design. When going into a constraints scenario dialog, you can
create a set of constraints that can be used to analyze your design
pre-layout, and/or to drive timing driven place-and-route. Multiple
constraint scenario dialogs can be open simultaneously to allow you
to easily view the constraint sets that are to being tested. Both Layout
and SmartTime Options allow for selection of saved scenarios, plus
you can import an SDC file into a specific scenario, or export a selected
scenario with an SDC file.
A constraint coverage report provides statistical data on the actual
constraint tests that are performed. The report shows the number of
constraints that are met, not met, or are untested. Supported checks
are: setup, hold, recovery, removal, and output. Adjustments can then
be made in SmartTime to ensure that more constraints are tested and
met.
SmartTime also includes a constraint checker that validates the constraints
in the database.
Timing Analysis
SmartTime provides a selection of analysis types that enable you
to:
- Find the minimum cycle time that does not result in a timing
violation
- Identify paths with timing violations
- Analyze delays of paths that have no timing constraints
- Perform inter-clock domain timing verification
- Perform maximum and minimum delay analysis for setup and hold
checks
To improve the accuracy of the results, SmartTime evaluates clock
skew during timing analysis by individually computing clock insertion
delays for each register.
SmartTime also checks the timing requirements for violations while
evaluating timing exceptions (such as multicycle or false paths).
SmartTime User Interfaces for Timing Analysis and Constraint Setting
