Design Probe Insertion
Probe insertion is a post-layout process that enables an IGLOO, ProASIC3, or Fusion designer to insert probes into the design and bring signals out to package pins on the device to evaluate and debug the design. Probe insertion has a minimal timing effect on the overall design and is a convenient way to quickly understand logic issues in any design. While testing a programmed devicethe user's design may have inherent logic errors due to inadequate simulation test coverage, or external signals arrived out of sequence, or timing setup and hold violations were ignored.
Probe insertion enables selection of internal nets anywhere in the design, connection of signals to unused pins, and running of incremental layout. Nets are selected and assigned probes using the "Generate Probed Design" feature available from the Designer Tools menu. If all package pins are already assigned, a used pin can be temporarily disconnected to enable connection of the probed signal to that pin. The re-routed design can then be programmed into the FPGA, where an external logic analyzer or oscilloscope can be used to view the activity of the probed signal. The package pins and port names are reported in Designer's log file. Once the evaluation is complete, the original saved layout file can be used if no design modifications are needed, or any necessary modifications can be made to the design so that layout can be run again. Post-layout probe insertion is faster than using Synopsys Identify Actel Edition (AE), which requires instrumentation of the design at the RTL level and running synthesis.
A simplified wizard available in Designer makes it easy to add, generate, edit, and delete probes in the design.
Key Features
- Directly insert probes into design after routing to evaluate switching activity
- Assign a signal to unused pin
- Incremental route minimally disturbs entire design
- Monitor activity with logic analyzer or oscilloscope
- Add, Edit, Delete probes
- Original layout is preserved
- Instrumentation of the RTL and running synthesis is not required
- Supports all IGLOO, ProASIC3 and Fusion families
User's Guides and Manuals
