SmartGen Core Configurator
Actel's SmartGen core generator enables you to access and configure "correct by construction" optimized common elements such as multiplexors, counters, memory elements, counters, and comparators for easy implementation into either a schematic or an HDL design. SmartGen supports the generation and configuration of all
Fusion peripherals within the Analog System Builder (ASB) and Flash Memory System Builders. The SmartGen ASB enables you to create analog functions such as voltage, current, temperature monitors, plus any number of other analog measurement systems for a Fusion-based system.
With SmartGen, simply select a core function from a large library, configure the core via a comprehensive visual configurator "dialog," and generate structural netlists in EDIF, VHDL, and Verilog. Furthermore, you can generate VHDL and Verilog behavioral models for most parameterized functions for use in simulation.
When used with Libero IDE, the SmartGen list of configurable cores is available as part of the Project Manager Catalog that also displays DirectCore IP cores, HDL Templates, Actel library macros, and Fusion busses. Simply browse and click on any SmartGen core title to open its configuration window and incorporate it into the Libero IDE project. Once configured and generated, Smartgen cores "components" are available in the Design Explorer and visible as part of a SmartDesign block system project.
When using standalone Designer, SmartGen opens to display a full SmartGen project, including core categories, varieties, versions, and brief descriptions, and shows what configured cores are already available as design source files.
SmartGen User Interface when Used with a Designer Only Installation
