SmartGen Core Configurator
Actel's SmartGen core generator enables you to access and configure "correct by construction" optimized common elements such as multiplexors, counters, memory elements, counters and comparators for easy implementation into either a SmartDesign, HDL text or schematic design for all Actel device families. The SmartGen core offering differs for each FPGA family. Not all cores are available for all FPGA families.
With SmartGen, simply select a core function from a large library, configure the core via a comprehensive visual configurator "dialog" and generate structural netlists in EDIF, VHDL and Verilog. Furthermore, you can generate VHDL and Verilog behavioral models for most parameterized functions for use in simulation.
When used with Libero IDE and Libero Standalone (SA), the SmartGen list of configurable cores is available as part of the Project Manager Catalog. For the Libero Catalog, SmartGen cores are automatically downloaded into your local PC vault based on the "www.actel-ip.com/repositories/SgCore" connection in the Project Manager Catalog/Options/Repositories dialog.
When using Designer without the Libero IDE Project Manager, SmartGen opens to display a full SmartGen project, including core categories, varieties, versions and brief descriptions, and shows what configured cores are already available as design source files. The SmartGen software is available in the Designer\bin folder in a Libero IDE or Libero SA installation.
SmartGen User Interface when Used with a Libero Standalone Installation
