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Application Notes

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  AC247: Macro Constraint Usage in ProASICPLUS Design Flow App Note  PDF 468 KB 1/2006
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  AC226: Designer Migration from Timer to SmartTime App Note  PDF 1.1 MB 7/2005
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  AC205: ProASICPLUS Timing Closure in Libero IDE v5.2 App Note  PDF 758 KB 5/2004
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  AC198: Clock Skew and Short Paths Timing App Note 
Information about calculating clock skew in Actel FPGAs
PDF 150 KB 3/2004
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  AC196: Static Timing Analysis Using Designer's Timer App Note  PDF 696 KB 1/2004
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  AC192: Floorplanning ProASIC/ProASICPLUS Devices for Increased Performance App Note  PDF 392 KB 11/2003
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  AC191: Conversion of Discontinued Programming Files (.DEF and .FUS) to Supported Format (.AFM) App Note  PDF 30 KB 10/2003
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  AC187: ProASIC and ProASICPLUS Timing Constraints App Note  PDF 234 KB 9/2003
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  AC186: ProASIC and ProASICPLUS Design-Flow Migration to Designer v5.0 App Note  PDF 265 KB 9/2003
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  AC179: Keeping Existing Physical Constraints Using Designer v5.0 App Note  PDF 122 KB 8/2003
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  AC152: Using Synopsys Design Constraints (SDC) with Designer App Note  PDF 120 KB 10/2001
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  AC122: Optimal Datapath Generation Using ACTgen App Note  PDF 124 KB 6/1997
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User's Guides and Manuals

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Other Guides

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License Information

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