Designer – Actel's Design Implementation Software

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Designer is Actel's powerful physical implementation software tool suite for all Actel FPGAs. After completing design entry and functional verification using Libero Integrated Design Environment (IDE) tools, import the resulting netlist into Designer to set timing constraints, run place-and-route, and perform timing analysis, power analysis, and program file generation.

For SmartFusion designs that extend into the FPGA fabric with logic design beyond the microprocessor subsystem (MSS), Designer is used to place-and-route and optimize the entire SmartFusion design.

For customers who already have their own design creation, synthesis, and simulation tools, a Libero Standalone (SA) license supports traditional Designer functionality, plus it offers SmartDesign and the Core Catalog, enabling the quick creation of simple FPGA designs or complex SoC processor and bus-based designs using SmartGen cores, Actel IP cores and user-generated HDL modules.

The Libero IDE Project Manager is also supported by the Libero SA license but its use is optional. Existing Designer licenses also support the features below.

Product Features

• Seamlessly compatible with:
  • Actel Libero IDE front-end design/verification tools and tool flows
  • Industry's most popular synthesis tools
• Support for established EDA standards such as Verilog/VHDL/EDIF/VITAL/SDF/SDC
• MultiView Navigator provides physical constraint editing plus cross-probing and other design viewing capabilities with the following tools:
  • ChipPlanner: device-level floorplanning tool
  • PinEditor: package pin assignment tool
  • I/O Attribute Editor: set characteristics of I/O pins
  • NetlistViewer: design schematic viewer
• Supports SmartFusion fabric designs
• Timing-driven and power-driven place-and-route
• Enhanced flows for further timing or power optimization
• Incremental routing supports in process design changes without disturbing previous layout
• Block flow design locks timing and placement for design and re-use support
• SmartPower provides comprehensive power analysis features to assist in low power optimization
• SmartTime static timing analysis and constraints management
• Post-route >probe insertion for design debug of flash devices
• FlashLock design security programming software
• Programming file generation supports Actel FPGA programming tools
• Full Tcl scripting support
• Actel simulation libraries
• Supported on Microsoft Windows and RedHat Linux operating systems

Note: A Libero SA/Designer installation and license does not include front-end design tools, Synplify Pro AE, ModelSim AE, or ViewDraw AE.

Designer User Interface