CoreConsole Information

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CoreConsole

IP Deployment Platform Simplifies Development
of System-Level Designs in Actel FPGAs

Introducing SmartDesign, the next generation CoreConsole "design creation" tool

Product Features

The CoreConsole IP Deployment Platform (IDP) and block stitcher has been developed to enable designers to quickly assemble system-level designs and to simplify the construction of a processor subsystem and assembly of IP blocks within a design. The CoreConsole IDP is a front-end design entry tool that enables IP blocks to be stitched together into synthesizable and simulatable RTL that can be exported into Actel's world-class Libero IDE FPGA development tool suite. The CoreConsole IDP enables users to focus on the system rather than individual components, allowing them to evaluate system-level performance earlier in the design process and reduce overall development time. The IP cores presently included in CoreConsole can be found on the DirectCore IP Cores page.

Key Features

Enables rapid assembly of system-level designs
IP deployment platform with secure IP vault
Supports IP block stitching and configuration
Intuitive, easy to use graphical user interface (GUI)
Users can add their own IP cores
Automatic system testbench generation
Includes configurable processor subsystem blocks

System Requirements

The minimum, recommended system requirements are listed below:

Platform	Processor	File System	Disk Space	RAM	Other
Windows XP Pro & Vista Business	1.0 GHz Pentium	NTFS, FAT32	400 MB	128 MB	CDROM, HTML browser, 1024 x 768 video resolution

Supported Platform

Microsoft Windows

Windows Vista Business

Windows XP Professional with SP2 (cumulative)

Licensing

CoreConsole IDP licenses are available for free. For more information and to receive your free license, visit Software Licenses and Registration System.

Note: Libero IDE Windows Disk-ID locked licenses contain a CoreConsole license and a basic set of DirectCore licenses, as noted on the CoreConsole IP Cores page.