Beginning with Libero IDE v8.4, the CoreConsole IP Deployment Platform has been replaced by SmartDesign.

Within the Libero IDE environment, SmartDesign provides powerful design entry features beyond CoreConsole for creating complex processor, bus-based designs, and more.

SmartDesign is a graphical block system design creation tool that provides a visual common platform where pre-designed HDL functions for processors, buses, DirectCore IP, SmartGen cores, Designer blocks, user IP, plus glue logic functions can be easily assembled, connected, and automatically abstracted to synthesis-ready HDL file to create a complete FPGA SOC. Actel recommends that SmartDesign be used all new processor and bus based designs. Learn more about SmartDesign.

• CoreConsole is still available to support designs-in-progress or design updates.

Cortex-M1 Design using SmartDesign