Advanced Electronic Design
Advanced Electronic Design (AED) was founded in 1997 to design digital
signal processing solutions for military applications. Today, AED provides
IP cores and complete solutions for customer designs implemented with FPGA
to ASICs. All of their designs are built from a generic Java Processor
(JAP) system. The JAP system includes the Java processor hardware IP, the
operating system (JOS) and development tools.
AED offers the following products:
- JAP Processor — The JAP processor supports two instruction
sets. First, it supports the Java byte-code instruction set and is able
to execute most of Java byte codes in 1 clock cycle. The Java language
is a high level object oriented language which is secured (dynamic verification,
exception processing, garbage collecting, etc.), portable (virtual machine)
and standard. The second instruction set supported by the JAP processor
is a native RISC instruction set which is able to execute classical native
languages such as C. The JAP architecture shares common resources in
the processor to execute both Java and RISC instruction sets.
The general features of the JAP are:
- 32-bit Harvard architecture
- 5-stage pipeline
- Instruction and data cache
- 7 interrupt lines and 1 non maskable interrupt (NMI)
- Java stack secured
- 25 000 instances
The JAP IP is delivered as a VHDL netlist and can be synthesized for
use in Actel FPGA devices. In the new ProASIC3 family Jap uses 8500 tiles
and runs at 40MHz.
- Borneo — Borneo is derived from the JAP solution and is
dedicated to color embedded graphical interfaces. Borneo combines the
JAP processor and a graphics accelerator to provide a complete solution
for the development of efficient embedded man machine interfaces (MMI).
The Java language is well suited to program graphical interfaces and
most graphical development frameworks are developed in Java (Eclipse,
etc.). Borneo is able to drive a large range of screens from 128x128
to 1280x800 in true color (16 Million colors).
- Jexar — Jexar is a powerful application that is derived
from AED's JAP solution. It is designed to support intensive arithmetic
computation. Initially designed for spatial applications, to accelerate
the intensive compute program execution, Jexar includes a full hardware
IEEE-754 (64 bits) floating point unit and an extended integer unit.
Both units are compliant with the Java specifications. A SEU (Single
Event Upset) and SET (Single Event Transient) tolerant version are also
available.
- Services — AED offers design services for:
- FPGA and ASIC design
- Software development
- System design
For additional information, contact AED at:
- Advanced Electronic Design
- 6 rue René Cassin
91300 MASSY
France
Phone: +33 (0) 1.69.30.43.67
Email: info@a-e-d.com
Web: www.a-e-d.com
