SynaptiCAD Sales Inc.
SynaptiCAD develops EDA tools that help engineers think critically
about their designs and offers a complete line of VHDL and Verilog
model generation, simulation, and timing diagram visualization tools.
SynaptiCAD's WaveFormer Lite is shipped with the Actel Libero Integrated
Design Environment (IDE) package and is used to generate test benches
from single timing diagrams. The package can be upgraded to WaveFormer
Pro to add Analog Signal Display and Interactive simulation for creating
the timing diagrams or TestBencher Pro to add multi-diagram test bench
and reactive model generation. SynaptiCAD also offers VeriLogger Extreme,
a fast compiled Verilog simulator.
WaveFormer
Pro is a revolutionary new rapid-prototyping EDA tool that helps
you design faster and with fewer mistakes. Upgrade WaveFormer Lite
to WaveFormer Pro and get analog signal display and digital timing
analysis feature that enables you to automatically determine critical
paths, verify timing margins, adjust for common delay effects, and
perform "what if" analysis to determine optimum clock speed.
WaveFormer Pro also lets you specify and analyze system timing and
perform RTL level simulation without the need for schematics or simulation
models. When your timing diagram is complete, you can then generate
digital stimuli for your favorite Verilog, VHDL, SPICE or gate-level
simulator. WaveFormer Pro has the ability to import and annotate
simulation and logic analyzer data for publication-quality design
documentation. Download WaveFormer Pro from www.syncad.com
TestBencher
Pro provides designers with a graphical environment for rapidly
generating and testing bus-functional models for VHDL, Verilog, and
SystemC. Where WaveFormer Lite generates testbenches using one timing
diagram, TestBencher allows multiple timing diagrams to be linked
together to generate bus functional models. Each timing diagram is
a reusable bus transaction and they can be applied to the model under
test using both specified and random data generation. TestBencher
Pro dramatically reduces the time necessary to develop test suites
by generating model code from language independent graphical timing
diagrams and automating the build process.
VeriLogger
Extreme is a completely new, high-performance compiled-code Verilog
2001 simulator that significantly reduces simulation debug time.
VeriLogger Extreme offers fast simulation of both RTL and gate-level
simulations with SDF timing information. VeriLogger Extreme supports
design libraries and design flows for all major ASIC and FPGA vendors.
VeriLogger Extreme also comes with BugHunter Pro, a graphical
Verilog/VHDL integrated development environment, which supports debugging
with all major HDL simulators. BugHunter supports source-level debugging,
a waveform compression engine for high-speed waveform dumping and
viewing, and graphical test bench generation features for rapidly
testing HDL models.
For information about pricing
and obtaining products or services, please contact SynaptiCAD directly.
Library Information
SynaptiCAD's WaveFormer Lite™ AE testbench tool is integrated
into Libero IDE. There are no libraries required for this tool.
For additional information, contact SynaptiCAD at:
- SynaptiCAD Sales Inc.
- 605 Alleghany St.
Blacksburg, VA 24060
USA
Tel: +1 800.804.7073
+1 540.953.3390
Fax: +1 540.953.3078
Email: sales@syncad.com
Web: www.syncad.com
