Aldec, Inc.
Aldec® Corporation is a industry-leader in electronic design and offers a patented technology suite including: design entry, HDL simulators, co-simulation, design rule checking, hardware-assisted verification, co-verification, IP Cores, DO-254 compliance tool sets, and engineering specialty solutions. Established in 1984, Aldec is a privately held company with continuous revenue growth and employs approximately 200 people worldwide. Corporate headquarters are located at 2260 Corporate Circle, Henderson, Nevada 89074. World Wide Web site: www.aldec.com.
Aldec Reprogrammable Prototyping
Aldec and Actel have joined together delivering an industry leading prototyping solution which allows on-the-fly design reprogrammability of flash-based prototypes. This solution provides an Aldec hardware adaptor compatible with RTAX-S that uses a reprogrammable ProASIC chip. In addition, an EDIF netlist converter is available, automating pin remapping between the RTAX-S design and flash-based architecture.
Features and Benefits:
- Allows RTAX-S prototyping with Actel flash devices
- Adaptor can be reprogrammed
- The prototype adaptor is footprint-compatible with RTAX4000S-CQ352 or RTAX2000S, RTAX1000S, and RTAX250S in CG624, CQ208, CQ256 and CQ352 packages
- JTAG connector/programming
- Automated device netlist conversion
- Automatic memory conversion
- Automatic physical design constraint (PDC) file conversion
DO-254 Compliance Tool Set (CTS)
The Aldec DO-254 CTS provides support for the "Design Assurance Guidance for Airborne Electronic Hardware" (DO-254/ED80) chapter 6.2 "Verification Process" and chapter 11.4 "Tool Assessment and Qualification Process". Aldec provides a fast and reliable verification process for assurance levels A, B, C, and D with a focus on increased testability in hardware together with the design requirements traceability.
Features and Benefits:
- Design verification in the target device
- In-Hardware verification performed at speed
- Same number of tests run in the target device as in the simulator with 100% test coverage assured
- Automated output waveform comparisons between the HDL simulation and in-hardware testing results
Active-HDL is a completely integrated FPGA design and verification solution, providing ease-of-use, advanced verification and debugging capabilities for today's most complex FPGA designs. A multi-vendor flow manager controls simulation, synthesis, and implementation for all devices from Actel and other FPGA vendors.
Features and Benefits:
- Graphical design entry including FPGA vendor primitives
- Mixed language HDL simulation
- Pre-compiled FPGA vendor libraries
- Automatic testbench generation
- Import legacy designs
- Code2Graphics and Graphics2Code
- DSP design and co-simulation with MATLAB®/Simulink®
- HTML and PDF design documentation
- Code coverage analysis and Linting
- Open IP encryption
Riviera-PRO is a proven high-performance, mixed-language simulation engine with advanced debugging tools for ASIC and FPGA design teams. Riviera-PRO supports VHDL, Verilog®, SystemVerilog, SystemC, C/C++, PSL, and OVA assertions from one common design environment. Riviera-PRO enables mixed RTL debugging, long regression testing, timing simulation, and electronic system level (ESL) verification.
Features and Benefits:
- Common-Kernel mixed language simulator
- IEEE standards support (VHDL, Verilog, SystemVerilog, SystemC)
- Universal HDL/SystemC code level debugging
- Assertion and coverage-based verification
- DSP/HDL algorithm co-simulation
- Script compatible with other HDL simulators
- Multi-Platform (32/64-bit Linux®, Solaris®, Windows®)
- Profiler
- Partner interfaces
- 64-bit computing
- Linting
- Simulate Synplicity-encrypted IP
CoVer_ActelMP7 is a Windows-based co-verification solution that enables engineers to perform hardware/software verification of Actel CoreMP7-based designs. It provides control and visibility for both the hardware and software engineering teams. The solution addresses hardware and software integration problems and translates into shorter design schedule, a lower project costs and all-in-one debugging capabilities for ARM-based systems.
CoVer_ActelMP7 integrates Active-HDL simulator with Aldec's hardware board based on Actel FPGA devices. The CoreMP7, memory, and standard peripherals reside in the hardware on the FPGA board. Aldec's patented software/hardware interfacing allows for the simulation and debugging in Active-HDL waveform viewer. The board is connected to the workstation through 32/64-bit to 33/66 MHz PCI slot providing easy use and high performance.
Library Information
Pre-compiled Actel libraries are provided within the Active-HDL tool
and also can be downloaded from Aldec's
support website.
Download Evaluation Software
Go to Aldec downloads for a free 20-day evaluation license of Active-HDL, Riviera-PRO, or ALINT.
For additional information, contact Aldec at:
- Aldec, Inc.
- 2260 Corporate Circle
Henderson, NV 89074
USA
Tel: 702.990.4400
Fax: 702.990.4414
Email: sales@aldec.com
Web: www.aldec.com
