Actel
Product Features Product Features Product Table Product Table IP & Solutions IP & Solutions Design Software Design Software Starter Kits & Programming Starter Kits & Programming Documentation Documentation
 Architecture Block Diagram    In the News    Related Information  

ProASIC3

The Low Power, Low Cost, High Performance FPGA Solution

The ProASIC3 families of flash FPGAs offer a breakthrough in power, price, performance, density, and features for today's most demanding high-volume applications. ProASIC3 devices support the ARM7™ and ARM® Cortex™-M1 soft processor IP cores, offering the benefits of programmability and time-to-market at costs as low as $0.99. The ProASIC3 families are based on nonvolatile flash technology and support 15 k to 3 M gates and up to 620 high-performance I/Os.

The ProASIC3 family includes:

  • ProASIC3
  • ProASIC3E
  • ProASIC3 for Automotive
  • M1 ProASIC3
  • M1 ProASIC3E
  • M7 ProASIC3
ProASIC3 Webcast
Actel News
 

Webcasts

 

Product Features

Back to top
Key Features
ProASIC3 Diagram
  • Low-power consumption
  • As low as $0.99 unit cost
  • Lowest total systems cost
  • 1.5 V support
  • Cost-optimized, reprogrammable, and nonvolatile
  • Supports 128-bit AES decryption for device configuration
  • Single chip and live at power-up
  • 1,024 bits of user flash memory
  • Advanced I/O structure
  • Soft ARM7 core support
  • Neutron immune
  • Available in automotive temperature grade (T-Grade)
Architecture Block Diagram
Product Table
ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000
ARM-Enabled CoreMP7               M7A3P1000
Cortex-M1         M1A3P250 M1A3P600 M1A3P1000
System Gates 15 k 30 k 60 k 125 k 250 k 400 k 600 k 1 M
Typical Equivalent Macrocells 128 256 512 1,024 - - - -
VersaTiles (D-Flip-Flop) 384 768 1,536 3,072 6,144 9,216 13,824 24,576
RAM kbits (1,024 bits) - - 18 36 36 54 108 144
4,608-Bit Blocks - - 4 8 8 12 24 32
FlashROM
(FROM) bits		 1 k 1 k 1 k 1 k 1 k 1 k 1 k 1 k
Secure (AES) ISP 1 No No Yes Yes Yes1 Yes1 Yes1 Yes1
PLLs - - 1 1 1 1 1 1
VersaNet Globals2 6 6 18 18 18 18 18 18
I/O Standards Std. &
Hot Swap		 Std. &
Hot Swap		 Std.+ Std.+ Std.+/
LVDS		 Std.+/
LVDS		 Std.+/
LVDS		 Std.+/
LVDS
I/O Banks (+JTAG) 2 2 2 2 4 4 4 4
Speed Grades -F, Std. -F, Std.,
-1, -2		 -F, Std.,
-1, -2		 -F, Std.,
-1, -2		 -F, Std.,
-1, -2		 -F, Std.,
-1, -2		 -F, Std.,
-1, -2		 -F, Std.,
-1, -2
Temperature Grades C, I C, I C, I, T C, I, T C, I, T C, I C, I C, I, T
Single-Ended I/O / Differential I/O Pairs
QN68 49              
QN132   81 80 84 87/193      
VQ100   77 71 71 68/13      
TQ144     91 100        
PQ208       133 151/34 151/34 154/35 154/35
FG144     96 97 97/24 97/25 97/25 97/25
FG256         157/383 178/38 177/43 177/44
FG484           194/38 235/60 300/74
ProASIC3E Devices A3PE600 A3PE1500 A3PE3000
ARM-Enabled Cortex-M1   M1A3PE1500 M1A3PE3000
System Gates 600 k 1.5 M 3 M
VersaTiles (D-Flip-Flop) 13,824 38,400 75,264
RAM kbits (1,024 bits) 108 270 504
4,608-Bit Blocks 24 60 112
FlashROM
1 k 1 k 1 k
Secure (AES) ISP 1 Yes Yes Yes
PLLs 6 6 6
VersaNet Globals2 18 18 18
I/O Standards Pro Pro Pro
I/O Banks (+JTAG) 8 8 8
Speed Grades -F, Std., -1, -2 -F, Std., -1, -2 -F, Std., -1, -2
Temperature Grades C, I C, I C, I
Single-Ended I/O / Differential I/O Pairs
PQ208 147/65 147/65 147/65
FG256 165/79    
FG324     221/110
FG484 270/135 280/139 341/168
FG676   444/222  
FG896     620/310
Notes:
  1. AES not available for ARM-enabled ProASIC3 devices.
  2. Six chip (main) and twelve quadrant global networks are available for A3P060 and above.
  3. The M1A3P250 device does not support this package.

IP and Solutions

Back to top

IP CoresSearch for ProASIC3 IP cores.

Technology Solutions
Low Cost Starting at $0.99, the world’s lowest cost FPGA solution offering industry-leading unit cost and lowest total system cost.
High Performance Enhanced, high-performance architecture up to 350 MHz operation and best-in-class logic utilization.
Single Chip Does not require additional configuration nonvolatile memory in order to load the device configuration data at every system power-up, which reduces cost and increases security and system reliability.
Secure ISP Supports built-in AES decryption engine and industry-leading flash-based AES-128 key for secure remote field updates over public networks with encrypted bitstream.
User Nonvolatile Memory 1,024 bits of on-chip, user accessible, nonvolatile FlashROM that can be used in diverse system applications.
Live at Power-Up Greatly simplifies system design, making the device available to perform critical system setup tasks and reduce bill-of-materials costs and PCB area.
Low Power Maximizes power savings with very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. Offers low dynamic power consumption.
Secure Utilizes a 128-bit flash-based lock and inherent flash technology features, providing the most impenetrable security for programmable logic designs. » More
Firm Errors Flash cell configuration element cannot be altered by high-energy neutrons and is therefore immune, unlike SRAM based FPGAs.
ARM7 Soft Core Uses industry-standard ARM7 with no upfront licensing fees and no royalties.

Design Software

Back to top

Libero IDEActel's Libero IDE offers the latest and best-in-class tools from leading EDA vendors such as Mentor Graphics, SynaptiCAD, and Synplicity. Libero IDE includes Actel's Designer software, which offers premier backend tools for physical implementation, including a comprehensive floorplanning capability via Actel's ChipPlanner tool. You can set timing constraints and perform timing analysis using SmartTime, a new and highly advanced environment for quickly setting and meeting timing objectives.

Starter Kits and Programming

Back to top
The ProASIC3 Starter Kit is a complete solution that enables quick evaluation of Actel ProASIC3 device families and design prototyping. The ProASIC3 Starter Kit comes in two versions. The first version is for prototyping, and the second, lower-cost version is for simple evaluation.

Device pre-programming is supported through Silicon Sculptor 3 and Silicon Sculptor II programmers. For in-system programming (ISP), the low-cost PC-based FlashPro3 programmer may be used.

For the ProASIC3 trace and debugging, Synplicity provides logic analysis software Identify Actel Edition (AE).

Related Information

Back to top