The Price/Performance Leader at 5.0V
Featuring very low power consumption and the industry's highest design security, MX FPGAs offer designers a reliable, single-chip ASIC alternative. Providing an efficient, flexible 5.0 V architecture, MX is an ideal platform for integrating your legacy PLDs into a single, low cost device. MX is a high-volume platform that enables solutions without compromising on cost and time.
Key Features
- High performance mixed-voltage solution
- PCI compliant
- Contains embedded dual-port SRAM modules
- Available in military and automotive temperature grades
| Device |
A40MX02 |
A40MX04 |
A42MX09 |
A42MX16 |
A42MX24 |
A42MX36 |
| Capacity |
| System Gates |
3,000 |
6,000 |
14,000 |
24,000 |
36,000 |
54,000 |
| SRAM Bits |
|
|
|
|
|
2,560 |
| Logic Modules |
| Sequential |
|
|
348 |
624 |
954 |
1,230 |
| Combinatorial |
295 |
547 |
336 |
608 |
912 |
1,184 |
| Decode |
|
|
|
|
24 |
24 |
| Clock-to-Out |
9.5 ns |
9.5 ns |
5.6 ns |
6.1 ns |
6.1 ns |
6.3 ns |
SRAM Modules
(64x4 or 32x8) |
|
|
|
|
|
10 |
| Dedicated Flip-Flops |
|
|
348 |
624 |
954 |
1,230 |
| Clocks |
1 |
1 |
2 |
2 |
2 |
6 |
| Maximum Flip-Flops |
147 |
273 |
516 |
928 |
1,410 |
1,822 |
| User I/O (maximum) |
57 |
69 |
104 |
140 |
176 |
202 |
| PCI |
|
|
|
|
Yes |
Yes |
| Boundary Scan Test (BST) |
|
|
|
|
Yes |
Yes |
| Speed Grades |
-F, Std.,
-1, -2, -3 |
-F, Std.,
-1, -2, -3 |
-F, Std.,
-1, -2, -3 |
-F, Std.,
-1, -2, -3 |
-F, Std.,
-1, -2, -3 |
-F, Std.,
-1, -2, -3 |
| Temperature Grades |
C, I, M, A |
C, I, M, A |
C, I, M, A |
C, I, M, A |
C, I, M, A |
C, I, M, A, B |
| Packages (by pin count) |
| PLCC |
44, 68 |
44, 68, 84 |
84 |
84 |
84 |
|
| PQFP |
100 |
100 |
100, 160 |
100, 160, 208 |
160, 208 |
208, 240 |
| VQFP |
80 |
80 |
100 |
100 |
|
|
| TQFP |
|
|
176 |
176 |
176 |
|
| CQFP |
|
|
|
|
|
208, 256 |
| PBGA |
|
|
|
|
|
272 |
| Technology Solutions |
 |
Does not require additional configuration nonvolatile memory in
order to load the device configuration data at every system power-up,
which reduces cost and increases security and system reliability. |
 |
Greatly simplifies system design, making the device available to
perform critical system setup tasks and reduce bill-of-materials
costs and PCB area. » More |
 |
Antifuse programmable technology is inherently protected against
reverse engineering and unauthorized duplication. » More |
 |
Antifuse configuration elements cannot be altered by high-energy
atmospheric neutrons and are therefore suitable for high reliability
applications at ground level and at aviation altitudes. » More |
The MX family of FPGAs is fully supported by Actel Libero IDE, a design management environment that guides the user through the FPGA design flow and provides seamless design tool integration as well as project, data file, and log file management. Libero IDE enables users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. The Actel Designer toolset is included for backend product implementation and programming file generation.
Actel offers a robust solution for both device debug and programming. For MX trace and debugging,
Silicon Explorer software is available.
Silicon Sculptor 3 is an FPGA programming tool that delivers high data throughput and promotes ease of use, while lowering the overall cost of ownership. The Silicon Sculptor 3 includes a high-speed USB 2.0 interface that allows a customer to connect as many as 12 programmers to a single PC.
