Cortex-M3: The ARM Processor for Embedded Applications

The ARM® Cortex™-M3 32-bit processor has been specifically developed to provide a high-performance, low-cost platform for a broad range of applications, including microcontrollers, automotive body systems, industrial control systems and wireless networking. With a balance between size and speed, Microsemi's free Cortex-M3 processor is included as a hard resource in Microsemi's SmartFusion2 and SmartFusion SoC FPGA families.

The SmartFusion2 implementation adds the Embedded Trace Macrocell (ETM) support and an 8KB Instruction Cache and operates at 166MHz, compared to 100 MHz in the SmartFusion devices.

The central core of the Cortex-M3 processor, based on a 3-stage pipeline Harvard bus architecture, incorporates advanced features such as hardware single-cycle multiply and hardware divide. The Cortex-M3 processor implementation of the Thumb®2 instruction set, plus features such as unaligned data storage and atomic bit manipulation, deliver world class 32-bit performance. The configurable Cortex-M3 processor connects to the Advanced High-Performance Bus (AHB), enabling designers to build their subsystem and easily add peripheral functionality.

In addition to SmartDesign and SoftConsole from Microsemi and RealView® tools from ARM, third-party vendors offer a vast range of supporting tools in the well-established ARM ecosystem, from compilers and debuggers to real-time operating system (RTOS) solutions.

The following manuals are available at the ARM Infocentre:

• Cortex-M3 Technical Reference Manual
• ARMv7-M Architecture Reference Manual
• ARMv7-M Architecture Application Level Reference Manual

The Definitive Guide to the ARM Cortex-M3 by Joseph Yiu is recommended as additional reading (ISBN: 978-0-7506-8534-4).

*Note ETM supported only in SmartFusion2 Implementation

The Cortex-M3 processor incorporates:

• A 32-bit processor core with low gate count and low latency interrupt processing
• RISC processor, 3-stage pipeline Harvard architecture, pipeline core incorporating branch speculation, single cycle multiplication, and hardware division, giving a Dhrystone benchmark of 1.25 DMIPS/MHz
• A nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low latency interrupt processing
• MPU is included
• Cortex-M3 processor is configured for SmartFusion2 MSS uses only little endian
• Auxiliary Control Register is included
• Multiple high-performance bus interfaces
• A debug solution with the optional ability to do the following:
  • Implement breakpoints and code patches
  • Implement watchpoints, tracing, and system profiling
  • Support printf() style debugging
  • Bridge to a trace port analyzer

Manufacturers of the Cortex-M3 processor integrated circuits are permitted some latitude in configuring a particular implementation of the Cortex-M3 processor delivered by ARM. Following are the implementation specifics in the SmartFusion2 device:

• Memory protection unit (MPU): This helps in creating protected and non-protected regions of memories.
• Flash patch break point (FPB)
• Data watchpoint and trace (DWT) unit
• Instrumental trace macrocell (ITM)
• Embedded trace macrocell (ETM) – SmartFusion2 Only
• Power-mode saving:
  • HCLK is gated off when in SLEEPING or SLEEPDEEP mode
  • SLEEPING and SLEEPDEEP signals are available at the FPGA fabric interface
  • Sleep mode extension handshake signals are available at the FPGA fabric interface
• Not all registers in the register bank are reset
• Endianness: Little endian only
• Auxiliary Control Register

The following configurations and optional features are not used in SmartFusion2 device:

• Wake-up Interrupt controller (WIC) is not included.
• Nested Vectored Interrupt Controller (NVIC): SmartFusion2 MSS is set to have 83 interrupts (including non-mask able interrupt).
• Interrupt priority levels: 16 priority levels (4 MSB bits in BASEPRI register) are implemented so BASEPRI register [7-4] are used for the priority setting and [3-0] are read as zeros.

Feature	SmartFusion	SmartFusion2
FPGA Fabric
System Gates	500,000	12 Million
Logic Elements	11,520 Tiles	120,348 4 input LUTs with DFF
Total RAM	108 Kbits	4,500 Kbits
4608 bit RAM Block	Yes	-
1K bit Micro Ram	-	Yes
18K bit Large Ram	-	Yes
18x18 Multiply Accumulate Blocks	-	Yes
Security
AES Bitstream encryption	Optional	Mandatory
Non volatile key storage	Yes	Yes
User Passkey	Yes	Yes
Encrypted Key	Yes	Yes
2nd optiobal user encryption and passkey set	No	Yes
Debug Pass Key	No	Yes
DPA Hardened	No	Yes
Bistream authentication	-	Yes
User access to AES Accelerator	No	Yes
User access to SHA Accelerator	-	Yes
User access to Random Number Generator	-	Yes
Device Certificate	-	Yes
Certificate of Conformance	-	Yes
CRI Pass Thru License	-	Yes
Microcontroller Subsystem (MSS)
Cortex-M3 processor with MPU	100MHz	166MHz
Embedded Trace Macrocell	-	Yes
8KB SEU Tolerant Instruction Cache	-	Yes
Flash (eNVM)	512 Kbytes	512 Kbytes
SRAM (eSRAM)	64 Kbytes	-
SECDED eSRAM	-	80 Kbytes
Fabric Interface Controllers	1	2
APB Fabric Interface Controller	-	1
Ethernet MAC	10/100	10/100/1000
SEU Tolerant Ethernet Buffers	-	Yes
HS USB OTG	-	1
SEU Tolerant USB Buffers	-	Yes
CAN 2.0A and B	-	1
SEU Tolerant CAN Buffers	-	Yes
I2C	2	2
SPI	2	2
SEU Tolerant SPI Buffers	-	Yes
16550 UART	2	-
Multi-Mode UART	-	2
SEU Tolerant MMUART Buffers	-	2
32-Bit Timer	2	2
Async Memory Controller	Yes	Yes
SDRAM Controller	-	Yes
LPDDR SECDED Controller	-	Yes
DDR2 SECDED Controller	-	Yes
DDR3 SECDED Controller	-	Yes
PDMA	Yes	Yes
High Performance DMA	-	Yes
PLL's	2	8
Main Oscillator (32 KHz to 20 MHz)	1	1
RTC Crystal Oscillator	Yes	Yes
Main Crystal Oscillator	Yes	Yes
RC Oscillator 1	100MHz	50MHz
RC Oscillator 2	-	1MHz
High Speed Serial Interfaces
SERDES 5 Gbps Lanes	-	16
PCIe Gen 2 5 Gbps Endpoints	-	4
User I/O
Maximum	204	574
Programmable Analog
ADCs(8-/10-/12-bit SAR)	3	-
DACs (8-/16-/24-bit sigma-delta)	3	-
Signal Conditioning Blocks (SCBs)	5	-
Comparators*	10	-
Current Monitors*	5	-
Temperature Monitors*	5	-
Bipolar High Voltage Monitors*	10	-

• - means not available.

For more information, visit the SmartFusion2 and SmartFusion web pages.

In addition to the on-chip AHB bus and communications infrastructure supporting the Cortex-M3, Actel offers a broad portfolio of IP cores for use in the FPGA fabric to implement custom design solutions. A wide range of IP cores are available FREE in the Libero and SmartDesign IP design tool.

To see a complete list of IP cores available in Libero, visit the Microsemi IP cores web page. Microsemi provides software drivers that ease the use of the cores for application developers, enabling development to focus on system capability instead of basic infrastructure. Microsemi's Firmware Catalog includes all of the available drivers and is installed with Libero.

Software developers will find support for SmartDesign and the Cortex-M3 in Microsemi's Eclipse-based SoftConsole, Keil™, IAR Systems® software development environments.

Libero System-on-Chip (SoC)

• Microsemi comprehensive FPGA design and development software
• Combines the latest design creation, physical implementation, and verification tools from leading EDA vendors

For more information, visit the Libero IDE web page.

SmartDesign

• Graphical block system design creation tool
• Create complete FPGA and system-on-chip (SoC) designs, including processors, Microsemi IP cores, standard library cores, user IP, and custom HDL
• Automatically creates synthesis-ready HDL
• Operates within Libero IDE

For more information, visit the SmartDesign web page.

SoftConsole

• Eclipse-based Microsemi processor software development environment
• Includes GNU C/C++ compiler and GDB debugger

For more information, visit the SoftConsole web page.

Microsemi FlashPro4 Programmer

Microsemi devices featuring the ARM Cortex-M3 processor are supported with in-system programming (ISP). Configuration data can be supplied through a standard JTAG interface from the on-board Cortex-M3, or from FlashPro4, or Silicon Sculptor 3. FlashPro4 offers extremely high performance through the use of USB 2.0 and is high-speed compliant for full use of the 480 Mbps bandwidth. Powered exclusively via USB, FlashPro4 provides a VPUMP voltage of 3.3 V for programming these devices.

SmartFusion Evaluation Kit

The SmartFusion Evaluation Kit offers a simple, low-cost way to try the world's only FPGA with hard ARM Cortex-M3 and programmable analog. The SmartFusion device contains on-chip flash and on-chip SRAM memory, and the kit adds additional SPI flash memory, an OLED display, and built in Ethernet connectivity. The evaluation kit board also includes LEDs, switches, and various voltage, current and temperature monitoring functions for analog experimentation on the board.

SmartFusion Development Kit

The SmartFusion Development Kit offers a full-featured development board so you can develop a complete system with the world's only FPGA with hard ARM Cortex-M3 and programmable analog. The SmartFusion device contains on-chip flash and SRAM memory, and the development kit board adds additional off-chip flash memory and SRAM/PSRAM in two voltage domains. The board can communicate via Ethernet and HyperTerminal. The development kit board also contains LEDs, switches, an OLED display and extensive analog resources, including voltage rail monitoring, current POT, temperature diodes and voltage sweeping using active bipolar prescalers (ABPS). Networking interfaces include Ethernet PHY, EtherCAT, CAN, UART, and RS485.