Actel
RTSX-SU RadTolerant FPGAs specifically designed for enhanced radiation performance are enhanced versions of Actel's commercial SX-A family of devices. Featuring SEU-hardened D-type flip-flops that offer the benefits of Triple Module Redundancy (TMR) without the associated overhead, the RTSX-SU family is a unique product offering for space applications. Manufactured using 0.25 µm technology at the United Microelectronics Corporation (UMC) facility in Taiwan, RTSX-SU offers levels of radiation survivability far in excess of typical CMOS devices.

Product Features

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Actel's RTSX-SU architecture, derived from the highly successful SX-A sea-of-modules architecture, has been designed to improve upset and total-dose performance in radiation environments with several enhancements, such as SEU-hardened flip-flops, wider clock lines, and stronger clock drivers. Designed in a sea-of-modules architecture, the entire floor of the FPGA is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing.
Key Features
  • 230 MHz system performance (310 MHz internal)
  • Very low power consumption (Up to 68 mW at Standby)
  • 3.3 V and 5.0 V mixed voltage
  • Configurable I/O support for 3.3 V/5 V PCI, LVTTL, TTL, and CMOS
    • 5 V input tolerance and 5 V drive strength
  • Secure programming technology prevents reverse engineering and design theft
  • 100% circuit resource utilization with 100% pin locking
  • Unique in-system diagnostic and verification capability with Silicon Explorer II
  • Low-Cost prototyping option deterministic, user-controllable timing
  • JTAG boundary scan testing in compliance with IEEE Standard 1149.1 — dedicated JTAG Reset (TRST) Pin
  • Highly reliable, nonvolatile antifuse technology
  • 32 k to 72 k ASIC gates (48 k to 108 k system gates)
  • Up to 360 user-programmable I/Os
  • Hermetically-sealed packages for space applications (CQFP, CCGA/LGA, CCLG)
Radiation Performance
  • SEU-Hardened registers eliminate the need to implement TMR
  • Immune to Single-Event Upsets (SEU) to LETTH > 40 MeV-cm2/mg
  • SEU Rate < E10–10 upset/bit-day in worst-case geosynchronous orbit
  • Up to 100 krad (Si) Total Ionizing Dose (TID) — parametric performance supported with lot-specific test data
  • Single-Event Latch-Up (SEL) immunity

Product Table

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Devices RTSX32SU RTSX72SU
Capacity
   Typical Gates 32,000 72,000
   System Gates 48,000 108,000
Logic Modules 2,880 6,036
   Combinatorial Cells 1,800 4,024
   SEU-Hardened Register Cells (Dedicated Flip-Flops) 1,080 2,012
Maximum Flip-Flops 1,980 4,024
Maximum User I/Os 227 360
Clocks 3 3
Quadrant Clocks 0 4
Speed Grades Std., -1 Std., -1
Temperature Grades B, E, M B, E
Package (by pin count)
   CQFP 84, 208, 256 208, 256
   CCGA   624
   CCLG 256  

IP and Solutions

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IP CoresSearch for RTSX-SU IP Cores.

Technology Solutions
OneChip is all you need. Does not require additional configuration nonvolatile memory in order to load the device configuration data at every system power-up, which reduces cost and increases security and system reliability.
Secure Antifuse programmable technology is inherently protected against reverse engineering and unauthorized duplication. » More
Firm Error Immune Antifuse configuration elements cannot be altered by high-energy heavy ions that abound in space and are therefore suitable for different types of space applications.
Live at Power-Up Greatly simplifies system design, making the device available to perform critical system setup tasks and reduce bill-of-materials costs and PCB area. » More

Design Software

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Libero IDEThe RTSX-SU family of FPGAs is fully supported by Actel Libero IDE, a design management environment that guides the user through the FPGA design flow and provides seamless design tool integration as well as project, data file, and log file management. Libero IDE enables users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. The Actel Designer toolset is included for backend product implementation and programming file generation.

Design Hardware

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Prototyping
A lower cost prototype solution is available for RTSX-SU devices that utilizes commercial SX-A devices. The prototyping solution has two main components:
  • A well-documented design flow that allows the customer to target an RTSX-SU design to the equivalent commercial SX-A device
  • Either footprint-compatible packages or prototyping sockets to adapt commercial SX-A packages to the RTSX-SU package footprints
Program & Debug
Programming support for RTSX-SU devices is provided through Actel's Silicon Sculptor 3, a PC-based programmer that delivers high data throughput and promotes ease of use, while lowering the overall cost of ownership. Actel offers a unique in-system diagnostic and verification capability with Silicon Explorer II.

Related Information

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