RT ProASIC®3 FPGAs are the first to offer designers of space-flight hardware a radiation-tolerant (RT), reprogrammable, nonvolatile logic integration vehicle. They are intended for low-power space applications requiring up to 350 MHz operation and up to 3 million system gates.

Unlike all of Actel's other radiation-tolerant, space-flight FPGAs, which use antifuse programming technology, devices in the RT ProASIC3 family use flash cells to store configuration information. Positive or negative charge stored on floating-gate transistors is used to hold pass transistors in either the "on" or "off" states, thereby opening or closing connections between routing tracks and logic resources. This use of flash-based interconnects present some unique opportunities and advantages to designers of space-flight electronic hardware:

• The flash cells are reprogrammable. This allows the designer to change the design of the FPGA without removing the FPGA from the board, making prototyping easier. It also allows for the possibility of in-flight reprogrammability, so that mission life can be extended by re-purposing the hardware to incorporate updated algorithms.
• The flash cells are nonvolatile. This means that flash-based FPGAs are standalone devices which do not require the provision of external code-storage devices, unlike SRAM-based FPGAs. This minimizes the board space used, and has an associated saving in mass.
• RT ProASIC3 FPGAs are operating almost at the instant of power-up, which is another advantage of the nonvolatility of the flash programming cells. There is no boot sequence required, as in SRAM-based FPGAs which need to download their configuration code from an external storage device.
• The flash cells do not exhibit single-event upsets in the presence of heavy ion radiation. Therefore no triple-chip redundancy to mitigate configuration upsets is required, unlike SRAM FPGAs.

Actel's RT ProASIC3 FPGAs are available in two densities, giving designers the opportunity to integrate large or medium-size designs into these single-chip, live-at-power-up devices.

Product Table

RT ProASIC3 devices use the same silicon design and process as the commercial UMC 0.13 µm ProASIC3EL family. RT3PE600L uses the same silicon as the A3PE600L, and RT3PE3000L uses the same silicon as the A3PE3000L. For more details on the architecture and design used by the RT ProASIC3 devices, refer to the ProASIC3L page.

RT ProASIC3 FPGAs are assembled in hermetically-sealed, ceramic packages, which are available as either Column Grid Array (CG, with Six Sigma solder columns attached) or Land Grid Array (LG, no solder columns attached). Qualification, inspection, assembly, and testing are performed in accordance with MIL-STD-883 Class B.

RT ProASIC3 FPGAs use the same silicon design and the same 0.13 µm process at UMC as their commercial equivalent ProASIC3EL parts. The ProASIC3 devices have been extensively tested for a variety of radiation effects. The main effects are summarized below. A set of detailed radiation reports is available on the Radiation and Reliability Data page.

Single-Event Effects (SEE)

• Single-Event Latch-Up (SEL)
  ProASIC3 devices have been tested in heavy ion environments with effective linear energy transfer (LET) rates of > 96 MeV-cm²/mg. No SEL events have been observed.
• Single-Event Upset (SEU)
  Heavy ion SEU events have been measured in logic tiles configured as D-type flip-flops, in embedded SRAM memory cells, and in phase-locked loops (PLLs). The embedded FlashROM nonvolatile memory has also been tested but did not exhibit any SEU to LET rates > 96 MeV-cm²/mg. Additionally, proton tests have been conducted on the flip-flops and SRAM memory. SEU results for both heavy ions and protons are tabulated below. The PLLs were observed to lose lock at low LET rates. The onset rate and saturation cross-section appears to be frequency-dependent.
  
  

  Feature	Test Limit	Onset LET	Saturation Cross-Section
  Configuration Flash Cells	96 MeV-cm2/mg Heavy Ions	No errors observed	No errors observed
  D-Type Flip-Flops	96 MeV-cm2/mg Heavy Ions	6 MeV-cm2/mg	2E-7 cm2 per flip-flop
  SRAM Memory	96 MeV-cm2/mg Heavy Ions	1 MeV-cm2/mg	4E-8 cm2 per memory bit
  FlashROM Memory	96 MeV-cm2/mg Heavy Ions	No errors observed	No errors observed
  D-Type Flip-Flops	63.5 MeV Protons		5E-14 cm2 per flip-flop
  SRAM Memory	63.5 MeV Protons		1E-13 cm2 per memory bit

• Single-Event Transient (SET)
  Heavy ion transients have been observed on the global clock networks and on the I/O banks. SET results are tabulated below.
  
  

  Feature	Test Limit	Onset LET	Saturation Cross-Section
  Global Clock	> 70 MeV-cm2/mg	4 MeV-cm2/mg	2E-6 cm2 per global clock network
  I/O Bank	> 70 MeV-cm2/mg	7 MeV-cm2/mg	2E-6 cm2 per I/O bank

• SEE Mitigation Strategies
  Mitigation of the observed single-event effects may be required, depending on the flight-critical nature of the application. If required, mitigation can be accomplished by the instantiation of triple-module redundancy (TMR) of the clock network, the I/O banks and the D-type flip-flops. Synthesis tools have the capability of generating triple-module redundant data paths. TMR is not the most efficient way of achieving mitigation in the combinatorial logic and the embedded SRAM memory. Alternative strategies exist for nonvolatile FPGAs, such as dual-redundant, combinatorial pathways using guard-gates and short delay elements. Such strategies are explained in more detail in the radiation reports.

Total Ionizing Dose

ProASIC3 devices have been tested for Total Ionizing Dose (TID) effects in both x-ray and gamma ray environments. Reports are available for both environments. Since the gamma ray data is usually of most interest to radiation effects scientists working on space-flight systems, the data presented on this page is applicable to only the gamma ray testing.

Two main TID effects are observed. The first effect is a degradation of propagation delay through the pass transistors that implement the connections between logic modules and routing tracks. This occurs as charge is deposited in the floating gates, causing them to become either more strongly programmed or less strongly programmed, depending on their original condition. The floating gates which become less strongly programmed are less able to hold the interconnect pass transistors in the "on" state, and this is observable as an increase in propagation delay through the pass transistors. An increase in propagation delay of 10% has been observed at gamma ray TID levels of 15 to 25 krad, depending on V_CCA. The Actel Designer development software includes a 10% propagation delay derating at 15 krad for designers who wish to account for this increase in propagation delay in their simulation and static timing analysis work.

The second TID effect observed concerns the programming circuits. The programming process includes a step where the amount of charge stored on a programmed floating gate is measured—referred to as "margining" because, in effect, the amount of margin beyond the minimum programmed charge level is measured. This is an essential step in the programming process, since without it the programming process cannot guarantee that each flash cell has received sufficient charge to remain reliably programmed over the lifetime of the device. The circuits performing the margining function begin to degrade at gamma ray TID levels in excess of 15 krad. For customers not requiring reprogramming of the device during space flight, this mechanism will not have any negative effect on the operation of the RT ProASIC3 FPGAs. However, for customers who wish to change the programming code of the device while it is in space, this effect requires that the final reprogramming of the RT ProASIC3 FPGA takes place before the part has received 15 krad of gamma total dose.

As with all other RT FPGAs from Actel, each wafer lot of RT ProASIC3 will be sample tested for TID effects in compliance with MIL-STD-883 Class B test method 1019. The results of the TID testing for each wafer lot will be published on the Radiation and Reliability Data page.

The RT ProASIC3 family of FPGAs is fully supported by Actel's Libero® Integrated Design Environment (IDE), a comprehensive FPGA development tool suite that offers the latest and best-in-class tools from leading EDA vendors such as Mentor Graphics®, SynaptiCAD, and Synplicity®. Libero IDE offers premier physical implementation tools and options for place-and-route, setting constraints, and analyzing timing. Libero IDE's Power-Driven Layout automatically reduces the power consumption of your RT ProASIC3 design, plus you can easily pinpoint sources of power consumption using SmartPower. SmartPower provides a hierarchical view of the entire design, as well as detailed views that enable you to quickly realize the component, location, and magnitude of power sources inside the design.

Prototyping

RT ProASIC3 devices are pin-compatible and timing-compatible with the commercial equivalent ProASIC3EL devices in Fine-Pitch Ball Grid Array (FG) packages. For example, to prototype a space-flight design intended for RT3PE600L-CG484B (RT3PE600L in the Column Grid 484 package), designers should use A3PE600L-FG484M (A3PE600L in the Fine Ball Grid 484 package). The use of the M version (military temperature range) ensures that timing can be verified in hardware across the full temperature range from –55°°C to 125°C. Since ProASIC3 FPGAs are reprogrammable, only a very small number of prototyping devices need be purchased.

Programmers

Device pre-programming is supported through Silicon Sculptor 3 programmers. For in-system programming (ISP), the low-cost PC-based FlashPro3 programmer may be used.