RTAX-S radiation-tolerant FPGAs offer industry-leading advantages for designers of space-flight systems. High performance and low-power consumption, true single-chip form factor, and live-at-power-up operation all combine to make RTAX-S the FPGA of choice for space designers. From concept to final integration and flight, Actel provides the tools and support to help you successfully integrate your space-flight application into RTAX-S radiation-tolerant FPGAs. Additionally, for space applications that have a need for a lower standby current, Actel offers RTAX-SL, the low-power grade option that has half the standby current of the standard product at worst-case conditions.

RTAX-S/SL offers high performance at densities of up to 4 million equivalent system gates and 840 user I/Os for space-based applications. The RTAX-S/SL family, the leading Actel product offering for space applications, features SEU-hardened flip-flops implemented without any user intervention, and offers the benefits of user-implemented triple module redundancy (TMR) without the associated overhead.

Key Features

• Highly reliable, nonvolatile antifuse technology
• 30 k to 500 k ASIC gates (250 k to 4 M system gates)
• Up to 540 kbits of embedded memory with optional EDAC protection
• Up to 840 user-programmable I/Os
• Total Dose: 300 krad (functional) and 200 krad (parametric)
• SEU less than 1E^-10 errors per bit-day (worst-case GEO)
• SEL immune to LET_TH in excess of 117 MeV-cm²/mg
• SEU immune to LET_TH > 37 MeV-cm²/mg
• Advanced packaging for space applications (CQFP and CCGA/LGA)
• Screening: E-Flow (Actel Extended Flow), B-Flow (Mil-STD-883B), and EV-Flow (Class V Flow processing as per MIL-PRF-38535)
• RTAX-SL: Low-power grade option with half the standby current of standard product at worst case conditions

Note:
* EV refers to the production flow developed by Actel that implements all of the steps specified by QML Class V, as defined in the MIL-PRF-38535.

The RTAX-S/SL radiation-tolerant FPGAs comprise a new feature-rich family based on the commercial Axcelerator architecture and are specifically designed for space applications. The high density gives designers the advantages of a flexible programmable platform on payload designs, which historically have required radiation-hardened ASICs (RH-ASICs). The increased on-chip functionality gives designers the flexibility to perform last minute design changes without incurring additional costs and without any impact on design time.

RTAX-S/SL offers higher density, higher performance, and more features than previous generations of Actel radiation-tolerant FPGAs. SEU-hardened flip-flops use built-in TMR, so they do not require user intervention and do not consume additional programmable logic gates for hardware implementation or host CPU machine cycles for software implementation. SEU-hardened flip-flops are not sensitive to place-and-route locations, thus preserving their SEU immunity.

The RTAX-S/SL family has hot-swap and cold-sparing capabilities, which enable a device to be turned off for minimal power consumption during long space missions and activated only when functionality is required for mission completion.

Actel has recently implemented enhanced procedures for the qualification and lot acceptance of the radiation-tolerant RTAX-S/SL antifuse FPGAs. These procedures are based on extended testing using highly perceptive designs that stress the antifuses within the product. There have been no antifuse faults to date. Actel will continue to life-test these products and use the data collected to enhance the reliability of the product. Current testing of the RTAX-S devices using both the Qualification Burn-In (QBI) and the Enhanced Antifuse Qualification (EAQ) tests now totals 1.8 million hours of life testing with no antifuse faults. With the data from the above testing, a failure in time (FIT) has been calculated based on the chi-square distribution, with a minimum upper confidence limit of 60% per JESD74 and an activation energy of Ea = 0.7 eV. The CMOS FIT rate is FIT = 11.8 at 55°C.

Radiation Performance

• Single-Event Effects
  • Testing performed at BNL and Texas A & M 2004
• SEL and SEDR
  • Testing performed up to LET_TH 117 MeV/cm²-mg (125° C)
  • No SEL or SEDR observed
  • No clock or control logic upset observed
• Single-Event Transient
  • High-frequency testing (with NASA Goddard Space Flight Center) up to 150 MHz—no anomalies found
• Logic Single-Event Upset (SEU)
  • Cross-section < 1E^-9 cm²
  • LET_TH > 37 MeV-cm²/mg
  • SEU per R-Cell < 4E^-11 Errors/bit-day (worst case GEO)
  • Better than the targeted 1E^-10 upsets/bit-day
• Memory SEU
  • Cross-section / word ~ 4E^-9 cm², LET_TH > 30 MeV-cm²/mg
    • EDAC operational, background scrubbing at 2 MHz
  • SEU < 1E^-10 upsets/bit-day (worst case GEO)
• Total Ionizing Dose
  • Initial results indicate suitability for vast majority of space missions
    • No parametric failure up to 200 krads (Si)
    • No functional failure up to 300 krads (Si)

Total Ionizing Dose (TID)

Total Ionizing Dose (TID) is caused by radiation due to charged particles and gammas in space. This radiation deposits energy by causing ionization in the material. The ionization can change the charge excitation, charge transport, bonding, and decomposition properties of the material, and therefore, the device parameters. Total dose is the cumulative ionizing radiation that an electronic device receives over a specified period of time. The damage is dependent on the amount of radiation and how long it took to accumulate the total dose and is expressed in Radiation Absorbed Dose (RAD). Actel publishes RTAX-S TID reports so that customers can use the radiation data when designing applications with high-reliability needs.

Single-Event Effects (SEE)

Ionizing radiation can cause unwanted effects in semiconductor devices. Energetic protons, neutrons, heavy ions, and alpha particles can strike sensitive regions of the transistor, causing various failures, or SEE, such as the following:

• Single-Event Upsets (SEUs), which occur when high-energy ionizing particles, such as heavy ions, alpha particles or protons, irradiate a circuit or pass through an integrated circuit, causing a disruption in the system logic.
• Single-Event Latch-Up (SEL) is a condition that causes a device to lose functionality due to a single-event-induced high current state. An SEL may or may not cause permanent device damage, but it does require power strobing of the device to resume normal device operations. Devices with low (< 37.5 MeV-cm²/mg) SEL LET_TH are considered unsuitable for space applications.
• Single-Event Transient (SET) upsets are caused by charges accumulated in reverse-biased junctions in CMOS digital circuits at higher frequencies

Actel publishes SEE test reports so that customers can take the data into consideration while designing space systems.

The RTAX-S/SL family of FPGAs is fully supported by Actel Libero® Integrated Design Environment (IDE), a design management environment that guides the user through the FPGA design flow and provides seamless design tool integration, as well as project, data file, and log file management. Libero IDE enables users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. The Actel Designer toolset is included for backend product implementation and programming file generation.

Prototyping

For the early development phase, functional verification, and a cost-effective way to prototype for RTAX-S/SL designs, Actel offers commercial Axcelerator products. Most RTAX-S/SL products have a footprint-compatible equivalent device that customers can use during prototyping. For those package types that do not have footprint-compatible Axcelerator equivalent devices, prototyping adaptors are offered that pin-map the Axcelerator devices to RTAX-S/SL package footprints.

Prototyping with RTAX-S PROTO Units

For final design verification, Actel offers the RTAX-S PROTO units that have the same footprint and timing characteristics as the flight unit. The RTAX-S PROTO units guarantee performance over the full military temperature range. These solutions offer tremendous savings in design time by eliminating design cycles, which translates into overall lower development costs.

Programmers

Programming support for RTAX-S devices is provided through Actel's Silicon Sculptor 3, a PC-based programmer that delivers high data throughput and promotes ease of use, while lowering the overall cost of ownership. RTAX-S adapter modules are also available.

Military and Aerospace Solutions

• RTAX-S/SL Prototyping with Flash Devices
• RTAX-S/SL LEON3 Development Board