RTAX-DSP space-flight FPGAs add embedded radiation-tolerant multiply-accumulate blocks to the tried-and-trusted industry-standard RTAX-S product family. The result is efficient utilization when implementing arithmetic functions, such as those encountered in DSP algorithms, without sacrificing reliability or radiation tolerance. RTAX-DSP integrates complex DSP functions into a single device without any external components for code storage and without multiple-chip implementations for radiation mitigation. This gives RTAX-DSP a significant advantage in power consumption and heat dissipation relative to SRAM-based FPGAs.

RTAX-DSP offers high performance at densities of up to 4 million equivalent system gates and 840 user I/Os for space-based applications. Embedded radiation-tolerant DSP mathblocks feature 18 bit x 18 bit multiply-accumulate blocks enabling efficient implementation of DSP building blocks such as finite impulse response (FIR) and infinite impulse response (IIR) digital filters, fast Fourier transforms (FFT) and inverse Fourier transforms (IFT), discrete cosine transforms (DCT), and Reed Solomon encoding algorithms. The RTAX-DSP family features up to 120 mathblocks, each capable of operating at 125 MHz over the full military temperature range (-55°C to 125°C), for a total throughput of 15 billion multiply/accumulates per second (15 GMACS).

RTAX-DSP Architecture

The RTAX-DSP family features SEU-hardened flip-flops for protection against the effects of heavy ion radiation in space. Up to 840 I/Os are available, accessed using Ceramic Quad Flat Pack, Land Grid Array, or Ceramic Column Grid Array packages.

Key Features

• Highly reliable, nonvolatile antifuse technology
• 250,000 to 500,000 ASIC gates (2 to 4 million system gates)
• Up to 120 DSP mathblocks with 125 MHz 18 bit x 18 bit multiply-accumulate
• Up to 540 kbits of embedded memory with optional EDAC protection
• Up to 840 user-programmable I/Os
• Total Dose: 300 krad (functional) and 200 krad (parametric)
• SEU less than 1E^-10 errors per bit-day (worst-case GEO)
• SEL immune to LET_TH in excess of 117 MeV-cm²/mg
• SEU immune to LET_TH > 37 MeV-cm²/mg
• Advanced CCGA and LGA packaging for space applications
• Screening: E-Flow (Microsemi Extended Flow), B-Flow (Mil-STD-883B), and Class V Flow processing as per MIL-PRF-38535

Product Table

Note: PROTO refers to prototype Unit, not for space flight or qualification of space-flight hardware.

RTAX-DSP FPGAs are assembled in hermetically-sealed, ceramic packages which are available as Ceramic Quad Flat Pack, Column Grid Array (CG, using Six Sigma copper-wrapped lead-tin solder columns), or Land Grid Array (LG, no solder columns attached). Qualification, inspection, assembly, and testing are to be performed in accordance with MIL-STD-883 Class B for QML Class Q and MIL-PRF-38535 for QML Class V . Extended Flow processing, incorporating additional screening beyond the requirements of Class B is also available.

RTAX-DSP devices are manufactured using the same 0.15 µm CMOS process as the RTAX-S and RTAX-SL FPGAs. The programming technology is identical. Consequently, RTAX-DSP devices will have the same radiation and reliability characteristics as the space-flight proven RTAX-S/SL devices. In addition, single event transient mitigation for registers are enhanced in RTAX-DSP to reduce the rate at which transient is captured at high frequency, such as those encountered in DSP applications.

The DSP Mathblock includes mitigation for both single-event transients in the combinatorial circuits and single-event upsets in the sequential circuits. In addition, RTAX-DSP uses the same radiation mitigation techniques as RTAX-S, with SEU-hardened registers and single-event mitigation in the clock and power-on reset circuits.

Read the Single-Event Effect Mitigation in RTAX-DSP Spaceflight FPGAs White Paper.

The RTAX-DSP family of FPGAs will be fully supported by Microsemi Libero® Integrated Design Environment (IDE), a design management environment that guides the user through the FPGA design flow and provides seamless design tool integration, as well as project, data file, and log file management. Libero IDE enables users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. The Microsemi Designer toolset is included for backend product implementation and programming file generation.

Prototyping

Prototype versions of the RTAX-DSP devices are available. These parts use the same silicon with the same timing as the space-flight qualified units, so that hardware timing verification across the full military temperature range (-55°C to 125°C) can be performed using the prototypes. The prototype devices also have the same pin assignment and mechanical footprint as the flight-qualified devices. However, while the prototype devices are assembled in ceramic packages, no MIL-STD-883 Class B processing is performed. Hermeticity is not tested nor guaranteed. Therefore, the prototype units are not intended for engineering qualification or space flight and should not be subjected to thermal vacuum testing nor should they be assembled onto boards intended for space flight.

Other prototyping solutions for RTAX-DSP space-flight FPGAs can be available through our partner Aldec. Contact Aldec for more information.

Click here to RTAX-DSP Prototyping Documentations

Programmers

Programming support for RTAX-DSP devices is provided through Microsemi's Silicon Sculptor 3, a PC-based programmer that delivers high data throughput and promotes ease of use, while lowering the overall cost of ownership. RTAX-DSP adapter modules are also available.