Microsemi

IP Module - PCI Express x1

The PCI Express x1 Endpoint is targeted to ProASIC3 silicon. It requires 53% of an A3P1000 (so it is compatible with AFS) and is a fully-compliant Master/Target solution. The PHY interface is 16 bits at 125 MHz. This solution is compatible with the external TI XIO1100 PHY chip.

PCI Express x1 implements the Logical sublayer including Scrambling/Descrambling, LTSSM State Machine, and Receive / Transmit Link Layer Packets. The core consists of the PHY Layer Interface, DLL Layer Interface, TLF Layer Interface, PCI Express Type C Register Set, and Custom User Register Set. A Standard SRAM interface is provided.

Standard deliverables include an Actel-targeted netlist or fully-synthesizable VHDL/Verilog RTL, Simulation models and testbench, Comprehensive user's guide, Timing constraint files, and Technical support.

To obtain more information or to obtain this core, please contact Gutz Logic

Key Features:

• Master and Slave PCI Express Endpoint Capability
• Full Compliance with PCI Express Base Specification
• PHY, DLL, and TL Layers
• Designed Specifically for the Actel ProASIC3 FPGA and TI XIO1100 PHY
• Uses 13,119 of 24,576 Tiles (53%) of an Actel ProASIC3 A3P1000 Device
• 16-bit 125 MHz PIPE Spec Interface PCI Type 0 Configuration Register Set
• Custom Configuration Register Set
• Link and Device Power Management
• PCIe Verilog Testbench Available
• PCIe Demo Board Available