IP Module - CoreAPB3
CoreAPB3 is an AMBA bus interface that is used to connect subsystem cores to Microsemi's soft processors. The bus interface is easy to use and fully compatible with the APB v3.0 protocol. The core is constructed to allows easy connection of IP cores in systems built around the ARM® Cortex™-M3, ARM Cortex-M1, Core8051s, or CoreABC processors. CoreAPB3 can be used with an APB3 master that does not have built-in APB address decoding to access APB (AMBA 2 or AMBA 3) peripherals, or in conjunction with the CoreAHBtoAPB3 bridge to connect an AHB or AHB-Lite bus fabric such as CoreAHBLite to access APB peripherals from an AMBA high-performance bus (AHB) or AHB-Lite master such as an Cortex-M3 or Cortex-M1.
- Implements an APB v3.0 bus fabric
- Supports up to 16 APB slave devices
- Auto-stitched to slave devices using SmartDesign IP design tool in Libero IDE
- Fully compatible with Cortex-M3, Cortex-M1, Core8051s, CoreABC and other APB3 IP cores
- Supports Microsemi's IGLOO/e, IGLOO PLUS, ProASIC3/E, ProASIC3L, SmartFusion2, SmartFusion, Fusion, RTAX-S/SL/DSP, RTSX-SU, RT ProASIC3, Axcelerator, SX-A, and ProASICPLUS families
- See the handbook for device utilization and performance details