Core8051s is an ASM51-compatible microcontroller core that can run programs written for the 8051. It contains the main 8051 core logic but no peripheral logic. Core8051s has an APB bus interface that can be used like the SFR bus to easily expand the functionality of the core by connecting it to existing APB IP peripherals. This allows users to configure the core with the peripheral functions (timers, UARTs, I/O ports, etc.) that they need for their application.
Features:
- High-performance 8-bit microcontroller
- 1 clock per instruction
- ASM51 (8051, 8031, 80C51) compatible
- Can be used with existing 8051 tools and code
- APB bus peripheral interface
- Optional MUL, DIV, DA instructions can be removed if not used to reduce core size
- Optional OCI debug block
- Supports Actel's IGLOO, ProASIC3, Fusion, Axcelerator and RTAX families
- See the handbook for utilization data for each supported device
Differences from Core8051:
- APB bus interface allows user selection of peripheral functionality
- Does not include fixed UART, timers, and I/O ports
- MUL, DIV and DA instructions are user-selectable
- Second data pointer is user-selectable
- Top 4 k of external data space is allocated to APB peripheral bus
- Only supports internal SFR registers
- See the handbook for more details
This core is available in the Libero IDE Catalog.
