IP Module - LEON3

LEON3 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The processor is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available from Aeroflex Gaisler AB under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application at a fraction of the cost of comparable IP cores. A fault-tolerant version (LEON3-FT) is available for System Critical applications.

Key Features:

• SPARC V8 instruction set with V8e extensions
• Advanced 7-stage pipeline
• Hardware multiply, divide and MAC units
• Separate instruction and data cache (Harvard architecture) with snooping
• Configurable caches: 1 - 4 sets, 1 - 256 kbytes/set. Random, LRR or LRU replacement
• Local instruction and data scratch pad rams
• SPARC Reference MMU (SRMMU) with configurable TLB
• AMBA-2.0 AHB bus interface
• Advanced on-chip debug support with instruction and data trace buffer
• Symmetric Multi-processor support (SMP)
• Power-down mode
• Robust and fully synchronous single-edge clock design
• Fault-tolerant and SEU-proof version available for space applications
• Extensively configurable
• Large range of software tools: compilers, kernels, simulators and debug monitors
• Support for Fusion, IGLOO, ProASIC3/E, Axcelerator, and RTAX-S Product Families