IP Module - CoreI2C

CoreI2C provides an APB-driven serial interface, supporting I²C, SMBus, and PMBus data transfers. Several Verilog/VHDL parameters are available to minimize FPGA fabric area for a given application. CoreI2C also allows for multiple I²C channels, reusing logic across channels to reduce overall tile count.

Key Features:

• Conforms to the Philips Inter-Integrated Circuit (I²C) v2.1 Specification (7-bit addressing format at 100 Kbps and 400 Kbps data rates)
• Supports SMBus v2.0 Specification
• Supports PMBus v1.1 Specification
• Data transfers up to at least 400 kbps nominally; faster rates can be achieved depending on external load and/or I/O pad circuitry
• Modes of operation configurable to minimize size
• Advanced Peripheral Bus (APB) register interface
• Multi-master collision detection and arbitration
• Own address and general call address detection
• Second Slave address decode capability
• Data transfer in multiples of bytes
• SMBus timeout and real-time idle condition counters
• IPMI 3 ms SCL low timeout
• Optional SMBus signals, SMBSUS_N and SMBALERT_N, controllable via APB IF
• Configurable spike suppression width
• Multiple channel configuration option
• Supports Actel IGLOO/e, ProASIC3/E, Fusion, RTAX-S, ProASIC^PLUS and Axcelerator FPGAs
  • See the handbook for device utilization and performance details

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