Actel

Actel IGLOO PLUS Low Power FPGAs
 
The low-power FPGA with enhanced I/O capabilities

Actel's IGLOO PLUS low-power FPGA family delivers unrivaled low-power and I/O features in a feature-rich programmable device, offering up to 64% more I/Os than the award-winning IGLOO family and supporting independent Schmitt trigger inputs, hot-swapping, and Flash*Freeze bus hold. Ranging from 30,000 to 125,000 gates, the 1.2 V to 1.5 V IGLOO PLUS devices have been optimized to meet the needs of I/O-intensive, power-conscious applications that require exceptional features.

Product Features

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Key Features
  • I/O-optimized FPGA
  • Ultra-low power in Flash*Freeze mode,
    as low as 5 µW
  • Low-power active capability
  • Small footprint and low-cost packages
  • Reprogrammable flash technology
  • 1.2 V to 1.5 V single voltage operation
  • Enhanced I/O features
  • Clock conditioning circuits (CCCs) and PLLs
  • Embedded SRAM and nonvolatile memory (NVM)
  • In-system programming (ISP) and security
Product Table
IGLOO PLUS Devices AGLP030 AGLP060 AGLP125
System Gates 30,000 60,000 125,000
Typcial Equivalent Macrocells 256 512 1,024
VersaTiles (D-Flip-Flops) 792 1,584 3,120
Quiescent Current (typical)
in Flash*Freeze Mode (µW)
5 10 16
RAM kbits (1,024 bits) 18 36
4,608-Bit Blocks 4 8
FlashROM Bits 1,024 1,024 1,024
Secure (AES) ISP Yes Yes
Integrated PLLs in CCCs1 1 1
VersaNet Globals2 6 18 18
I/O Standards IGLOO PLUS IGLOO PLUS IGLOO PLUS
I/O Banks (+JTAG) 4 4 4
Maximum User I/Os 120 157 212
Speed Grades Std. Std. Std.
Temperature Grades C, I C, I C, I
Single-Ended I/Os3
CS201 (8x8 mm) 120 157  
CS281 (10x10 mm)     212
CS289 (14x14 mm) 120 157 212
VQ128 (14x14 mm) 101    
VQ176 (20x20 mm)   137  
Notes:
  1. AGLP060 in CS201 does not support the PLL.
  2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
  3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one.

For a wider range of logic densities and features, refer to the low-power IGLOO or IGLOO nano FPGAs.

I/O Metrics and Capabilities

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IGLOO PLUS low power FPGA offers the industry's best power-, area-, logic- and feature-per-I/O ratios in a programmable device, delivering 6X better static power consumption, a 50% reduction in dynamic power consumption, a 2X improvement in I/O density, and as much as 2.7X the logic density compared with competitive programmable logic devices in a similar package.

IGLOO PLUS low-power FPGA solutions offer up to 16X better power per I/O. Assuming a design requires 100 I/Os, the AGLP030 device has 120 I/Os and consumes 5 µW versus the roughly 60 µW of the nearest competitive solution.

Power per I/O Comparison (30K System Gates) for IGLOO PLUS Low Power FPGAPower per I/O Comparison (60K System Gates) for IGLOO PLUS Low Power FPGA

The cost-effective IGLOO PLUS devices offer the following I/O features:

  • Four I/O banks that support varying voltage levels
  • A wide selection of I/O standards
  • Schmitt trigger inputs for greater noise immunity
  • Hot-swappability for direct system connection while powering up
  • Flash*Freeze bus hold, which allows users to hold the I/O states while in Flash*Freeze mode

IGLOO Family Resources

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Related Information

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