Ultra-Low-Power FPGAs with Enhanced I/O Capabilities
Actel's IGLOO PLUS family delivers unrivaled low-power and I/O features in a feature-rich programmable device, offering up to 64% more I/Os than the award-winning IGLOO family and supporting independent Schmitt trigger inputs, hot swapping, and Flash*Freeze bus hold. Ranging from 30,000 to 125,000 gates, the 1.2 V to 1.5 V IGLOO PLUS devices have been optimized to meet the needs of I/O-intensive power-conscious applications that require exceptional features.
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Key Features
- I/O-optimized FPGA
- Ultra-low power in Flash*Freeze mode,
as low as 5 µW
- Low-power active capability
- Small footprint packages
- Reprogrammable flash technology
- 1.2 V to 1.5 V single voltage operation
- Enhanced I/O features
- Clock conditioning circuit (CCC) and PLL
- Embedded SRAM and nonvolatile memory (NVM)
- In-system programming (ISP) and security
Product Table
| IGLOO PLUS Family |
AGLP030 |
AGLP060 |
AGLP125 |
| System Gates |
30 k |
60 k |
125 k |
| Typcial Equivalent Macrocells |
256 |
512 |
1,024 |
| VersaTiles (D-Flip-Flops) |
792 |
1,584 |
3,120 |
Quiescent Current (typical)
in Flash*Freeze Mode (µW) |
5 |
10 |
16 |
| RAM kbits (1,024 bits) |
- |
18 |
36 |
| 4,608-Bit Blocks |
- |
4 |
8 |
| FlashROM Bits |
1 k |
1 k |
1 k |
| Secure (AES) ISP |
- |
Yes |
Yes |
| Integrated PLLs in CCCs |
- |
1 |
1 |
| VersaNet Globals1 |
6 |
18 |
18 |
| I/O Standards |
IGLOO PLUS |
IGLOO PLUS |
IGLOO PLUS |
| I/O Banks (+JTAG) |
4 |
4 |
4 |
| Speed Grades |
-F, Std. |
-F, Std. |
-F, Std. |
| Temperature Grades |
C, I |
C, I |
C, I |
| Single-Ended I/Os2 |
| CS201 (8x8 mm) |
120 |
157 |
|
| CS281 (10x10 mm) |
|
|
212 |
| CS289 (14x14 mm) |
120 |
157 |
212 |
| VQ128 (14x14 mm) |
101 |
|
|
| VQ176 (20x20 mm) |
|
137 |
|
- Notes:
-
- Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
- When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the
number of single-ended user I/Os available is reduced by one.
For a wider range of logic densities and features, refer to the ultra-low-power IGLOO family FPGAs.
IGLOO PLUS offers the industry's best power-, area-, logic- and feature-per-I/O ratios in a programmable device, delivering 6X better static power consumption, a 50% reduction in dynamic power consumption, a 2X improvement in I/O density, and as much as 2.7X the logic density compared with competitive programmable logic devices in a similar package.
IGLOO PLUS solutions offer up to 16X better power per I/O. Assuming a design requires 100 I/Os, the AGLP030 device has 120 I/Os and consumes 5 µW versus the roughly 60 µW of the nearest competitive solution.
The cost-effective IGLOO PLUS devices offer the following I/O features:
- Four I/O banks that support varying voltage levels
- A wide selection of I/O standards
- Schmitt trigger inputs for greater noise immunity
- Hot-swappable for direct system connection while powering up
- Flash*Freeze bus hold, which allows users to hold the I/O states while in Flash*Freeze mode
Search for IGLOO PLUS IP Cores.
IGLOO PLUS low-power flash FPGAs are ideal for the portable market—offering low
active and static power consumption, ultra-low power mode support, small-footprint
packages, low cost, and improved I/O metrics and capabilities. To learn more about Actel's offering in the portable market, refer to the Portable Solutions web page.
A wide variety of LCD displays with rapidly changing display technologies available in the market. To meet the needs of short design cycle time to integrate newer display devices, Actel offers a wide range of flexible Display Solutions with IGLOO PLUS ultra-low-power flash FPGAs.
| Technology Solutions |
 |
Starting at 5 µW, IGLOO PLUS devices offer lowest static power, Flash*Freeze technology, and multiple low-power modes, achieving the lowest system power. » More |
| Low Cost |
Offers industry-leading unit cost and the lowest total system cost through integration of high number of I/Os and feature-rich FPGA capabilities. » More |
 |
Does not require additional configuration nonvolatile memory in order
to load the device configuration data at every system power-up, which
reduces cost and increases security and system reliability. |
 |
Greatly simplifies system design, making the device available to
perform critical system setup tasks and reducing bill-of-materials (BOM)
costs and PCB area. » More |
 |
Utilizes a 128-bit flash-based lock and inherent flash technology
features, providing the most impenetrable security for programmable
logic designs. » More |
 |
Flash cell configuration element cannot be altered by high-energy
neutrons and is therefore immune, unlike SRAM-based FPGAs. » More |
| Secure ISP |
Supports a built-in AES decryption engine and industry-leading flash-based
AES-128 key for secure remote field updates over public networks with
encrypted bitstream. |
| Small Footprint |
Wide selection of small sized packages optimizes logic and I/O design
needs while minimizing board size. |
| User Nonvolatile Memory |
1,024 bits of on-chip, user-accessible, nonvolatile FlashROM can
be used in diverse system applications. |
The IGLOO PLUS family is completely supported by Libero IDE using power-conscious design flows. Libero IDE takes the already low static and dynamic power features of IGLOO PLUS devices and enables you to further reduce power consumption using automatic Power-Driven Layout (PDL). The default selection for IGLOO PLUS devices uses 1.2 V I/Os for single power supply operation and 5 pF output loading. In addition, SmartPower's comprehensive and in-depth analysis capabilities pinpoint power consumption details throughout the design, so you can evaluate and edit the design where possible to reduce power consumption to an absolute minimum. Power profiles and battery life estimation are also featured for optimizing your IGLOO PLUS design for portable applications. A Flash*Freeze management flow in Libero IDE allows you to easily define and set the state of I/Os as the device enters the Flash*Freeze mode, to ensure the desired functional requirements for the design are met.
You can migrate your ProASIC3 designs to attain the low-power benefits of IGLOO PLUS, or, as for any Actel FPGA design, you can easily create new designs from the start. Learn more about Libero IDE flows and tools.
The IGLOO PLUS Starter Kit will be available in June 2008 and will provide complete evaluation solutions for examining both the low-power capabilities and the enhanced I/O features of the IGLOO PLUS device family, including preservation of the I/O state during Flash*Freeze.
Device pre-programming is supported through Silicon Sculptor 3 and Silicon Sculptor II programmers. For in-system programming (ISP), the low-cost PC-based FlashPro3 programmer may be used.
For IGLOO PLUS trace and debugging, the Identify Actel Edition (AE) logic analysis software from Synplicity will provide embedded debug capbilities.
