"I wanted to let you know that I did manage to find the problem with my Actel design, thanks to that ProbePilot that you brought in to us. The problem was a logic design error and not a timing problem. I was using some flip-flops to latch some status information that determines when a [down] counter is supposed to be reloaded (the specific count value). Unfortunately, I had recently made a design change and also introduced this bug. These flip-flops were getting updated on count 5, but the register will store count values ranging from -8 to +7. I had failed to initialize the register on power-up, so if it defaulted to either +6 or +7, my logic would be unable to update that register, since count 5 would never get reached. Since the design is a phase locked loop, it is important that this "terminal count" register gets updated to make the output track the input. Unfortunately, this problem did not appear until now because most chips just happen to power up with this register set to a value less than or equal to +5, allowing it to function normally. I would not have been able to find this simple error without that ProbePilot (I would have wasted time looking in the wrong places). It would have taken considerable design analysis (on paper), some "debug" designs (bring internal signals out pins), and a lot of time. Thanks!"