In-System debugging with Identify Actel Edition (AE) allows the Actel FPGA designer to quickly find and correct functional design bugs by probing internal signals of the design directly from the hardware at the system speed. The probed signals can be viewed directly onto the RTL view for easy interpretation of the data. It offers an advanced triggering mechanism that focuses on a certain area of the design and sets breakpoints in RTL.

Debugging Directly in RTL

• Conveniently allows selection of signals and code branches within RTL for sampling and/or triggering easily and quickly.
• Full support of all HDL design types (Verilog, VHDL or mixed language)
• Automatically adds the debug logic to the design
• Adds pipelined debug logic so there is minimal or no timing impact on original design

Complex Trigger Mechanisms and Automation

• Gather only the data you need using unique and complex triggering mechanisms
• Trigger on an event, a series of events, pulse width, or an absence of an event after a period
• Trigger from one clock domain and trigger sampling in another domain
• Supports TCL-based command line interface that allows automation of instrumentation or debug via scripts

Debugging at Full Speed

• Allows debugging of the design or storing the results from the FPGA running at speed
• Uses the built-in JTAG ports and/or user-selected pins for JTAG interface
• Results are stored on-chip in RAM blocks
• Allows rapid debug of results and the ability to get useful data with less debug logic for heavy utilized FPGAs. Provides immediate feedback on area used for debug logic.
• Allows faster iteration. Design changes are made to the device from Identify AE environment using incremental compile.
• Capture data from any number of signals or depth depending on available area within the FPGA

Display and Record of Results

• Annotates data directly to the source RTL and you can scroll by clock, back and forward in time
• Displays data in RTL source as symbolic data or enumerated data type rather than bit-level, ideal for state machines
• The captured data can be displayed in waveform viewers for viewing in a time-based format
• Allows export of debug vectors that can be used for simulation
• All nodes are tagged with a sample or trigger icon. Code branch statements (e.g. CASE or IF statements) are marked as breakpoints.

The following block diagram shows the debug flow. Before synthesis, the RTL design is instrumented using Identify AE Instrumentor. Instrumentation is a process of creating a debuggable HDL version of the design. This enables you to set the sample signals, trigger points for conditional sampling, and trigger breakpoints for allowing specific event-driven sampling of the signals within the design. The Identify AE Debugger then communicates with this debuggable design and captures the operation of the device via the flash device programmer. You can view the sampled signal values directly in the RTL or on a waveform viewer.

Identify AE may be used with the following devices:

• Fusion
• ProASIC3
• ProASIC^PLUS

Identify AE may be used with the following programmers:

• FlashPro3
• FlashPro Lite
• FlashPro

	Identify AE v2.4.1a Quick Start Guide		349 KB	11/2006	Click on the to rate this document
	Identify AE v2.4.1a Reference Manual		800 KB	11/2006	Click on the to rate this document
	Identify AE v2.5A Release Notes		256 KB	10/2007	Click on the to rate this document
	Identify AE v2.4.1a Tutorial		405 KB	11/2006	Click on the to rate this document
	Identify AE v2.4.1a User's Guide		1.7 MB	11/2006	Click on the to rate this document
	Tutorial for Using Identify® with Libero® Integrated Design Environment (IDE)		1.9 MB	5/2006	Click on the to rate this document
	ProASICPLUS Starter Kit User's Guide & Simple Tutorial		3.1 MB	12/2004	Click on the to rate this document