Designer Probe Insertion
Probe insertion is a post-layout process that enables an IGLOO® Series, ProASIC®3 Series, SmartFusion, or Fusion designer to insert probes into the design and bring signals out to the FPGA package pins to evaluate and debug the design. While testing a programmed device, the user's design may have inherent logic errors due to inadequate simulation test coverage, external signals that arrived out of sequence, or ignoring of timing setup and hold violations.
Probe insertion enables selection of internal nets anywhere in the design, connection of the selected signals to unused pins, and running of incremental layout to manage the physical connection to the pin. Nets are selected and assigned probes using the Generate Probed Design feature available from the Designer Tools menu. If all package pins are already assigned, a used pin can be temporarily disconnected to enable connection of the probed signal to that pin. The re-routed design can then be programmed into the FPGA, where an external logic analyzer or oscilloscope can be used to view the activity of the probed signal. The package pins and port names are reported in Designer's log file. Once the evaluation is complete, the original saved layout file can be used if no design modifications are needed, or any necessary modifications can be made to the design so that layout can be run again.
Probe insertion has a minimal timing effect on the overall design and is a convenient way to quickly understand logic issues in any design. Post-layout probe insertion is faster than using Synopsys® Identify® AE which requires instrumentation of the design at the RTL level and then running synthesis, layout, and device programming.
The Designer Probe Insertion feature is available from the Libero® Integrated Design Environment (IDE) Designer toolbar.
FlashPro On-Chip Debug
FlashPro on-chip debug enables the designer to inspect specific blocks within IGLOO, ProASIC3, SmartFusion, and Fusion family devices via the JTAG interface. On-chip debug features allow the designer to view the programmed contents of embedded FlashROM, nonvolatile memory (NVM), and analog blocks to determine if the data that is actually programmed into these blocks agrees with the pre-programming design parameters. This feature is helpful in the rare event when corruption occurs between the original design file creation and device programming or for final design analysis prior to the FPGA system testing or production.
FlashPro on-chip debug reads the FlashROM data from the programmed FPGA device and automatically compares the data to the programming database (PDB) file generated by Libero IDE. Any mismatch between the device data and the design file is automatically highlighted for the user in the FlashROM inspection interface window.
FlashPro on-chip debug reads the NVM content from the programmed FPGA device and displays the data. The designer can compare the content of the device data to the data from the PDB programming file. This read-only feature displays the programmed NVM data for each user client or for each NVM page address. It can also detect corruption on a per page basis so the designer can quickly locate the problematic areas.
On-chip debug allows the designer to perform a number of inquiries of the programmed SmartFusion and Fusion analog block attributes, including inspection of the analog block data on a channel-by-channel basis. The programmed FPGA device data can be compared to the analog block configurations generated by Libero IDE. Any mismatches are highlighted for the user.
FlashPro on-chip debug also supports viewing of device status information, such as device state, security settings, and power supply voltages supplied to the FPGA.
Launch FlashPro on-chip debug with the Verify Design Details button on the FlashPro software tool interface.
Synopsys Identify AE
On-chip debugging with Synopsys Identify AE allows the Actel FPGA designer to quickly find and correct functional design bugs by probing internal signals of the design directly from the flash FPGA at the system speed. The probed signals are inserted into the RTL and can be viewed directly as part of the RTL view for easy interpretation of the data. An advanced triggering mechanism focuses on a certain area of the design and sets breakpoints in RTL. Identify AE currently supports IGLOO Series, ProASIC3 Series and mixed signal FPGAs, SmartFusion and Fusion devices, through the FlashPro4, FlashPro3 and FlashPro Lite programmers.
Debugging Directly in RTL
- Conveniently allows selection of signals and code branches within RTL for sampling and/or triggering easily and quickly
- Provides full support of all HDL design types (Verilog, VHDL or mixed language)
- Automatically adds the debug logic to the design
- Adds pipelined debug logic so there is minimal or no timing impact on original design.
Complex Trigger Mechanisms and Automation
- Gather only the data you need using unique and complex triggering mechanisms
- Trigger on an event, a series of events, pulse width, or an absence of an event after a period
- Trigger from one clock domain and trigger sampling in another domain
- Supports TCL-based command line interface that allows automation of instrumentation or debug using scripts.
Debugging at Full Speed
- Allows debugging of the design or storing the results from the FPGA running at speed
- Uses the built-in JTAG ports and/or user-selected pins for JTAG interface
- Results are stored on-chip in RAM blocks
- Allows rapid debug of results and the ability to get useful data with less debug logic for heavily utilized FPGAs. Provides immediate feedback on area used for debug logic.
- Allows faster iteration. Design changes are made to the device from Identify AE environment using incremental compile.
- Captures data from any number of signals or depth, depending on available area within the FPGA.
Display and Record of Results
- Annotates data directly to the source RTL and you can scroll by clock, back and forward in time
- Displays data in RTL source as symbolic data or enumerated data type rather than bit-level; ideal for state machines
- The captured data can be displayed in waveform viewers for viewing in a time-based format
- Allows export of debug vectors that can be used for simulation
- All nodes are tagged with a sample or trigger icon. Code branch statements (for example, CASE or IF statements) are marked as breakpoints.
The following block diagram shows the debug flow. Before synthesis, the RTL design is instrumented using Identify AE Instrumentor. Instrumentation is a process of creating a debuggable HDL version of the design. Instrumentation of the design can be done using Identify either within the Synplify Pro AE synthesis tools, or standalone after importing the HDL design file. This enables you to set the sample signals, trigger points for conditional sampling, and trigger breakpoints for allowing specific event-driven sampling of the signals within the design. The Identify AE Debugger then communicates with this debuggable design and captures the operation of the device via the flash device programmer. You can view the sampled signal values directly in the RTL or on a waveform viewer.
Actel Silicon Explorer II
Imagine an integrated desktop suite of diagnostic tools that enables real-time observability of internal programmable logic nodes without affecting the timing, loading, or fanout of a design. Actel has made this kind of verification a reality with its Silicon Explorer II, a revolutionary diagnostic and verification tool kit for FPGA design verification.
Silicon Explorer II shortens the FPGA design verification process by providing a tightly integrated suite of tools and capabilities that enable rapid isolation of functional and timing problems—there's no need to re-layout, recompile, or redo any part of your design to complete the verification process. By removing the guesswork associated with trial and error methods of system verification, Silicon Explorer II saves weeks of effort and gives precise control over the verification process.
Once your design has been placed and routed using Actel's Designer software FPGA development tools, you can connect Silicon Explorer II and launch the Silicon Explorer software, which graphically displays the internal nets of your design. By a simple point-and-click, you are allowed to simultaneously select and examine up to two internal nodes. With Axcelerator®, you can select four internal nodes. The software displays the logic activity in real time, essentially turning your PC into an 18-channel logic analyzer and allowing you to verify your design node-by-node. To test additional nodes, you simply select them on the displayed list.
Key Features
- Supports all Actel antifuse devices
- Dynamic access into internal nodes without design re-layout
- User-friendly graphical user interface for viewing and analysis
- Supports 2.5 V, 3.3 V, and 5.0 V boards
- PC-hosted, 18-channel logic analyzer with up to 100 MHz asynchronous sampling rate
- Four levels of triggering
- Serial port connection — no plug-in cards
- Free software updates
- Supports Microsoft® Windows® XP
Silicon Explorer Hardware
| Hardware |
Vendor |
Part Number |
Comment |
| Silicon Explorer II |
Actel |
SILICON-EXPLORER II |
Internal debug tool, includes PC-hosted logic analyzer |
| Ribbon Cable Assembly |
Actel |
RIBBON & BREAKOUT CABLES |
Connects probe to header mounted on the PC board with a 16-pin connector |
| Flying Lead Cable Assembly |
Actel |
SI-EX-TCA |
Used for logic analyzer probes |
