For the 'Always On' Society
With a focused combination of features, eX can meet all
of your power, speed, package, and price requirements. Optimized for wired
and mobile e-appliances, eX enables designers to use a flexible single-chip
FPGA for their traditional low-density ASIC requirements without the long
lead times and costly NRE charges.
Key Features
- Low power consumption
- Live at power-up
- 2.5 V, 3.3 V, and 5.0 V mixed-voltage operation with 5.0 V input tolerance
and 5.0 V drive strength
- Up to 100% resource utilization with 100% pin locking
- Fuselock secure programming technology prevents reverse engineering
and design theft
- Available in automotive temperature grades
| Device |
eX64 |
eX128 |
eX256 |
| Capacity |
| System Gates |
3,000 |
6,000 |
12,000 |
| Typical Gates |
2,000 |
4,000 |
8,000 |
| Register Cells |
| Dedicated Flip-Flops |
64 |
128 |
256 |
| Maximum Flip-Flops |
128 |
256 |
512 |
| Combinatorial Cells |
128 |
256 |
512 |
| Maximum User I/Os |
84 |
100 |
132 |
| Global Clocks |
| Hardwired |
1 |
1 |
1 |
| Routed |
2 |
2 |
2 |
| Speed Grades |
-F, Std., -P |
-F, Std., -P |
-F, Std., -P |
| Temperature Grades* |
C, I, A |
C, I, A |
C, I, A |
| Package (by
pin count) |
| TQFP |
64, 100 |
64, 100 |
100 |
| CSP |
49, 128 |
49, 128 |
128, 180 |
Note: *
Refer to the eX Automotive Family FPGAs datasheet for details on automotive
temperature offerings.
| Technology Solutions |
 |
Does not require additional configuration nonvolatile memory in order
to load the device configuration data at every system power-up, which
reduces cost and increases security and system reliability. |
 |
Greatly simplifies system design, making the device available to perform
critical system setup tasks and reduce bill-of-materials costs and PCB
area. » More |
 |
Antifuse programmable technology is inherently protected against reverse
engineering and unauthorized duplication. » More |
 |
Antifuse configuration elements cannot be altered by high-energy atmospheric
neutrons and are therefore suitable for high reliability applications
at ground level and at aviation altitudes. » More |
The
eX family of FPGAs is fully supported by Actel Libero
IDE, a design management environment that guides the user through the
FPGA design flow and provides seamless design tool integration as well
as project, data file, and log file management. Libero IDE enables users
to integrate both schematic and HDL synthesis into a single flow and verify
the entire design in a single environment. The Actel Designer toolset
is included for backend product implementation and programming file generation.
The antifuse architecture is one-time programmable (OTP)
by design and devices are not in-system programmable. Device programming
is supported through the
Silicon
Sculptor 3 series of programmers, which include a high-speed USB 2.0
port. Up to twelve Silicon Sculptor 3 programmers may be connected to a single
PC. Silicon Sculptor 3 also provides extensive hardware self-testing along
with integrity test. For real-time debugging,
Silicon
Explorer II can be used to sample the built-in probe signals of the antifuse
architecture.
