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Axcelerator
» Documentation
Datasheets
Application Notes
Product Briefs
Product Information Brochures (PIB)
Power Calculator
Datasheets
Axcelerator Family FPGAs
v2.6
General Description
(pages 1-14, PDF, 403 KB)
Detailed Specifications
(pages 1-92, PDF, 1.1 MB)
Packaging
(pages 1-114, PDF, 762KB)
BGA Ball Maps
(ZIP, 200 KB)
2.3 MB
12/2005
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Packaging Data
Hermetic Package Mechanical Configuration
24 KB
11/2003
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Package Mechanical Drawings
(v10.5)
4.4 MB
6/2008
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Package Thermal Characteristics and Weights
50 KB
10/2006
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Application Notes
AC163: Axcelerator Carry-Connect Macros App Note
121 KB
1/2003
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AC164: Axcelerator Family Memory Blocks App Note
155 KB
1/2003
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AC170: Prototyping RTAX-S Using Axcelerator Devices App Note
134 KB
4/2003
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AC173: Differences Between RTAX-S/SL and Axcelerator App Note
63 KB
5/2003
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AC175: Axcelerator Family PLL and Clock Management App Note
179 KB
6/2003
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AC177: Implementing Multi-Port Memories in Axcelerator Devices App Note
Source Code
(ZIP, 12 KB, 07/04)
191 KB
7/2003
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AC182: Axcelerator I/O Selection Guide App Note
371 KB
8/2003
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AC183: Using Global Resources in Actel's Axcelerator Family App Note
126 KB
8/2003
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AC184: Migrating from Engineering Silicon to Production Devices for the Axcelerator Family App Note
152 KB
8/2003
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AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note
115 KB
3/2004
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AC204: Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment App Note
82 KB
5/2004
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AC209: Axcelerator Family Footprint Compatibility App Note
45 KB
7/2004
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AC210: Laser Range Finder Using Actel’s Axcelerator FPGA App Note
Design File
(ZIP, 345 KB, 07/04)
1.5 MB
7/2004
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AC211: 32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA App Note
Design File
(ZIP, 1.2 MB, 07/04)
657 KB
7/2004
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AC212: Designing a SuperClock with an Axcelerator Device App Note
Design File
(ZIP, 130 KB, 09/04)
419 KB
9/2004
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AC217: IEEE Standard 1149.1 (JTAG) in the Axcelerator Family App Note
238 KB
2/2005
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AC218: Using Axcelerator RAM as Multipliers App Note
390 KB
2/2005
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AC228: EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller App Note
730 KB
8/2005
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AC249: I/O Features in Axcelerator Family Devices App Note
Relative Pin Locations
(ZIP, 341 KB, 11/04)
1.2 MB
1/2006
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AC273: Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs App Note
– Applies to EDAC Core from Libero IDE v7.1 and Older
EDAC Core from Libero IDE v7.1 or Earlier
(ZIP, 41KB, 07/04)
263 KB
7/2006
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AC288: Using LVDS for Actel's Axcelerator and RTAX-S/SL Devices App Note
676 KB
10/2006
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AC319: Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs App Note
– Applies to EDAC Core from Libero IDE v7.2 and Newer
EDAC Core from Libero IDE v7.2
(ZIP, 45 KB, 06/06)
707 KB
2/2008
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Product Briefs
Axcelerator Family FPGAs Product Brief
161 KB
1/2005
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Axcelerator Evaluation Platform
51 KB
8/2003
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Product Information Brochures (PIB)
Axcelerator Family FPGAs Product Brochure
483 KB
8/2003
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Total System Cost Brochure
430 KB
3/2008
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Axcelerator Starter Kit Brochure
1.1 MB
11/2004
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Total System Power Brochure
495 KB
4/2008
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Single-Event Effects in FPGAs
313 KB
10/2007
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The Importance of Design Security Brochure
248 KB
4/2005
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Power Calculator
AX and RTAX-S Power Calculator
134 KB
10/2007
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