Actel
Product Features Product Features Product Table Product Table IP & Solutions IP & Solutions Design Software Design Software Starter Kits & Programming Starter Kits & Programming Documentation Documentation

Axcelerator

First for Speed and Performance. Accept Nothing Less.

Product Features

Back to top
The latest antifuse FPGA family offered by Actel, Axcelerator offers high performance and unprecedented design security at densities of up to 2 million equivalent system gates.

Utilizing the Actel AX architecture, Axcelerator devices have several system-level features, such as embedded SRAM (with embedded FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic.

Based upon 0.15 µm, seven-layers-of-metal CMOS antifuse process technology, Axcelerator devices offer a level of performance previously only available in ASIC technology.

Key Features
  • 350 MHz system performance
  • 500+ MHz internal performance
  • 500+ MHz embedded FIFOs
  • PLL output up to 1 GHz and 8 PLLs per device
  • 6 levels of logic at 156+ MHz
  • 1.5 V, 1.8 V, 2.5 V, and 3.3 V mixed-voltage operation
  • 8 I/O banks per device
  • 8 global clocks per device
  • 4.5 kbits variable-aspect RAM blocks with built-in FIFO control
  • Intelligent low power operation
  • Secure programming technology prevents reverse engineering and design theft
  • Available in military temperature grades

Product Table

Back to top
Device AX125 AX250 AX500 AX1000 AX2000
Capacity (in Equivalent System Gates) 125,000 250,000 500,000 1,000,000 2,000,000
   Typical Gates 82,000 154,000 286,000 612,000 1,060,000
Modules
   Register (R-cells) 672 1,408 2,688 6,048 10,752
   Combinatorial (C-cells) 1,344 2,816 5,376 12,096 21,504
   Maximum Flip-Flops 1,344 2,816 5,376 12,096 21,504
Embedded RAM/FIFO
   Number of Core RAM Blocks 4 12 16 36 64
   Total Bits of Core RAM 18,432 55,296 73,728 165,888 294,912
Clocks (Segmentable)
   Hardwired 4 4 4 4 4
   Routed 4 4 4 4 4
PLLs 8 8 8 8 8
I/Os
   I/O Banks 8 8 8 8 8
   Maximum User I/Os 168 248 336 516 684
   Maximum LVDS Channels 84 124 168 258 342
   Total I/O Registers 504 744 1,008 1,548 2,052
Speed Grades Std., -1, -2 Std., -1, -2 Std., -1, -2 Std., -1, -2 Std., -1, -2
Temperature Grades C, I C, I, M, B C, I, M, B C, I, M, B C, I, M, B
Package
   CSP 180        
   PQFP   208 208    
   BGA       729  
   FBGA 256, 324 256, 484 484, 676 484, 676, 896 896, 1152
   CQFP   208, 352 208, 352 352 256, 352
   CCGA/LGA       624 624

IP & Solutions

Back to top

IP CoresSearch for Axcelerator IP Cores.

Technology Solutions
OneChip is all you need. Does not require additional configuration nonvolatile memory in order to load the device configuration data at every system power-up, which reduces cost and increases security and system reliability.
Live at Power-Up Greatly simplifies system design, making the device available to perform critical system setup tasks and reduce bill-of-materials costs and PCB area. » More
Secure Antifuse programmable technology is inherently protected against reverse engineering and unauthorized duplication. » More
Firm Errors Antifuse configuration elements cannot be altered by high-energy atmospheric neutrons and are therefore suitable for high reliability applications at ground level and at aviation altitudes. » More
Target Applications
  • Consumer: Smartphones, GPS, high-end digital cameras, PDA, wireless gadgets, portable media players
  • Industrial: Point of sale, scanners, portable printers, RFID readers, portable radios, portable test and measurement equipment
  • Medical: Dental, medical instrumentation, defibrillators, insulin pump
  • Automotive: Car RF tag, instrumentation controls
  • Computing: Modules for laptops, PCMCIA cards
  • Telecomm: Wired and wireless electronics with high performance requirements
  • Military/Aerospace: Flight computers, mission computers, weapon systems, radar control systems

Design Software

Back to top

Libero IDEThe Axcelerator family of FPGAs is fully supported by Actel Libero IDE, a design management environment that guides the user through the FPGA design flow and provides seamless design tool integration as well as project, data file, and log file management. Libero IDE enables users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. The Actel Designer toolset is included for backend product implementation and programming file generation.

Starter Kits and Programming

Back to top
The Axcelerator Starter Kit is a complete solution, enabling quick evaluation and design prototyping of the Actel Axcelerator family. The kit includes the following:
  • Evaluation board with a pre-programmed PQ208 socketed AX250 Axcelerator device
  • Actel Libero IDE Gold
  • Power supply
  • User's guide including PCB schematics
  • Sample design

Other Axcelerator Development Kits & Boards

Actel's Silicon Sculptor II, a single-site programmer driven via a PC-based GUI, provides programming support. Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer tools, enables designers to examine any of the internal nodes of a device operating in a prototype or a production system.

For Axcelerator trace and debugging, Silicon Explorer software is available.

Related Information

Back to top