SRAM and FIFOs ProASIC3 devices have embedded dual-port SRAM and FIFO blocks
along the north and south sides of the device. Each variable-aspect-ratio
SRAM block is 4,608 bits in size. Available memory configurations are:
256x18, 512x9, 1kx4, 2kx2, or 4kx1 bits. The individual blocks have
independent read and write ports that can be configured with different
bit widths on each port. Dedicated FIFO control logic enables flexible
and efficient FIFO implementations.
VersaTile The ProASIC3 low power VersaTile elements allow synthesis
and mapping tools to use any tile as a three-input look-up table equivalent,
a D-flip-flop, or latch (with or without enable). ProASIC3 devices
with VersaTiles offer an abundance of registers so you can often choose
a smaller device and still meet register requirements.
Advanced I/O Standards
ProASIC3 devices support up to 19 advanced I/O standards:
Cold sparing I/Os
700 Mbps LVDS-capable DDR I/Os
Up to 8 different I/O banks per chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8
V / 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V input
Differential I/O Standards: LVPECL and LVDS, BLVDS, M-LVDS support
Voltage-Referenced I/O Standards (ProASIC3E only): GTL+2.5 V
/ 3.3 V, GTL2.5 V / 3.3 V, HSTL Class 1 and 2, SSTL2 Class 1 and
2, SSTL3 Class 1 and 2
Registered I/Os
Hot-swap compliant I/Os
Programmable slew rate and drive strength on outputs
Programmable delay, weak pull-up/down
Schmitt trigger option on inputs (ProASIC3E only)
Pin compatibility across a given package
Charge Pumps ProASIC3 devices can be programmed from a single 3.3 V supply
voltage. If remote programming is not required, ProASIC3 devices can
be run off a single 1.5 V supply.
FlashROM (FROM) ProASIC3 flash FPGAs include user flash memory. One kbit of
flash memory, arranged in eight 128-bit pages, allows for diverse applications
support, such as device serialization, secure application key storage,
revision control, and selective feature enabling.
Routing Structure ProASIC3 provides millions of flash cell switches and an abundance
of hierarchical routing resources, enabling extensive design and routing
flexibility.
VersaNet (segmented global) routing allows high-fanout nets to traverse
small or large areas of the ProASIC3 devices with low skew and flexibility.
The VersaNet network is used automatically by the software tools to
route clocks and high-fanout nets.
JTAG (IEEE 1532) ProASIC3 devices use industry-standard JTAG programming (IEEE
1532). In addition, ProASIC3 devices support board-level JTAG (IEEE
1149) I/O boundary scan.
PLL and CCC ProASIC3 devices have six Clock Conditioning Circuits (CCCs)
with up to six PLLs.
Wide input frequency range (fIN_CCC) = 1.5 to 350
MHz
Output frequency range (fOUT_CCC) = 0.75 to 350 MHz
