Actel

SoftConsole v2.1 Release Notes

(Jan 31, 2008)

Thank you for your interest in Actel's SoftConsole v2.1.

What's New

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  • SoftConsole v2.1 now supports embedded software development and hardware debugging targeting the Core8051s microcontroller.
  • The Cortex™-M1 Debug Sprite has a number of fixes included to improve both the reliability and speed of communication between the GDB debugger and the Cortex-M1 target using the UJTAG interface.
  • Separate Eclipse plugins now exist for CoreMP7, Cortex-M1, and Core8051s; the Zylin Embedded CDT plugin is still provided for backwards compatibility with existing projects.
  • SoftConsole is comprised of the following elements:
    • Eclipse Platform (and Java Runtime)
      • Eclipse IDE v3.2
      • Eclipse CDT (C/C++ Development Tools) v3.1
      • Zylin Embedded CDT plug-in v2.0.6
      • Sun Java J2SE Runtime v5.0
    • CodeSourcery GNU Toolchain for ARM Processors 2007q1-21 Release
      • GCC v4.2
      • GDB v6.6.50
      • Binutils v2.17
      • GNU make v3.81
    • 8051 Development Tools
      • SDCC Small Device C Compiler v2.6.3 for 8051 Targets
      • CodeSourcery Tools for 8051 1.0-7 Release
        • GDB v6.6.50
        • Binutils v2.17
        • CodeSourcery omf2elf 1.0-7
    • Hardware target debug support tools — the following tools sit between GDB and the relevant target processor in order to facilitate hardware-based debugging by translating between GDB Remote Serial Protocol and target processor specific JTAG/debug commands/responses:
      • CoreMP7: FS2 In-Target System Analyzer for ARM Processor Cores v1.2.0
      • Cortex-M1: CodeSourcery ARM Debug Sprite v1.0-5 Patch 1
      • Core8051s: Actel C8051 Debug Sprite v1.0

System Requirements

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Supported Platforms
Microsoft Windows - U.S. Version
  • Windows XP (XP Professional only) with SP2
Minimum System Requirements
Microsoft Windows XP
  • 1.0 GHz Pentium class processor
  • FAT32 or NTFS file system recommended
  • 400 MB available on disk
  • 128 MB system RAM
  • CDROM drive
  • HTML browser
  • 1024 x 768 video resolution
Software Environment
  • SoftConsole v2.1 requires that SoftConsole v1.0, SoftConsole v1.1, and SoftConsole v2.0 be uninstalled. The installer will not proceed if it detects a previous version installed.
  • SoftConsole requires that the FlashPro programming software and drivers are installed. The installer will check for Libero Integrated Design Environment (IDE) v7.3 or later or FlashPro v5.0 or later, and will not continue if neither is present. It is recommended that you install the latest versions of the Libero IDE software (which bundles the FlashPro software and drivers) and/or the standalone FlashPro programming software.

Licensing

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The individual licenses for the elements that make up SoftConsole are presented during the installation process for your review.

Known Limitations and Workarounds

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General
  • Writing a value to memory in the Memory pane of the SoftConsole IDE will take place with the hardware only one byte at a time. Thus, setting a particular address to have a particular 32-bit value will involve asking GDB to write four individual bytes. For some target designs, addresses are used assuming a single write will take place of all four bytes. In particular, APB memory may depend upon this behavior, where you only need the lower 8 bits of the 32-bit word involved. Until this is fixed in a future release, it is possible to make sure only a single one-byte write takes place for any given address: right-click in the memory region you want to modify and select Format. In the Format dialog, change the column size from 4 to 1, and click OK. This change will need to be made for each distinct memory monitor or window in your project if you need to change the width of your reads and writes.
  • SoftConsole is currently only supported in the creation and use of a Managed C Project; while it is technically possible to use a Standard C Project, there may be issues in attempts to debug your resulting program.
Cortex-M1 Target
  • The GDB debugger only supports talking to hardware for the Cortex-M1. Its internal simulator does not yet work for this target, but will be corrected in a future release.
Core8051s Target
  • To display the different memory spaces of the Core8051s in the Memory Monitor view, you will need to set some higher bits on the 16-bit address of the location in question:

    Memory Space Address Format Example
    XDATA 0x00xxxx 0x00120c
    DATA, including SFRs in upper 128 bytes 0x4000xx 0x40004a
    CODE 0x80xxxx 0x8000f3
    IDATA Not supported  

    Note: You should not set these bits in any address references in your program code.
  • The Core8051s GDB debugger and Actel C8051 Debug Sprite do not yet support indirect internal memory reads/writes (IDATA) in the Memory Monitor view. The lower 128 bytes share the same physical memory with directly addressed internal data memory (DATA), so they can still be viewed. However, the upper 128 bytes cannot be viewed. Also, the stack uses the IDATA memory space and so may not be debugged if the stack grows into the upper 128 bytes.
  • Viewing the APB region of XDATA memory is restricted to just the 1st byte of each 4-byte location, regardless of the APB data width configured in the Core8051s. As a possible work around, you can observe the XWBn and XRBn SFRs when APB transactions are occurring.
  • In the Memory Monitor view, if you attempt to write a value in the top 4k (0xF000-0xFFFF) of CODE memory, the action will also write to the corresponding address in XDATA memory.
  • Not all of the Special Function Registers (SFRs) are displayed in the Register View while debugging; only the accumulator "a", the "b" register, and the data pointer "dptr" are included with the other more traditional registers. To see other SFRs, you will need to use the Memory Monitor view, reading DATA memory in the upper 128 bytes (0x80—0xFF, or specifically 0x400080—0x4000FF as used in the view itself).
  • The Register View will also include values for some pseudo-registers specific to SDCC:
    • spx – stack pointer in XDATA memory
    • bpx – frame pointer in XDATA memory
    • bp – frame pointer in DATA memory
    These are used by SDCC when you enable its use of a Pseudo Stack. In the properties for your project, select C/C++ Build and under SDCC Compiler, select Memory Options and click Pseudo Stack (--xstack).
  • When debugging for the Core8051s, if you try to look at the (unsupported) Keil 'xbp' register (shown as "?c_xbp"), you will see an error on the console:
    mi_cmd_var_create: unable to create variable object
    This message can be safely ignored and will be fixed in a future release.
  • There is no way to create an ELF-format debuggable application as a release build for the Core8051s target. The result of a release build is an Intel HEX (*.ihx) file, which will need to be appropriately loaded onto your target.
  • To enable the large memory model, you need to select it for both the compiler and the linker. If you only change the compiler's, you will get errors at link-time.
    To enable the large memory model:
    1. Select your project, right-click and select Properties.
    2. Choose C/C++ Build.
    3. The SDCC Compiler's Memory Options can be changed from the pull-down menu.
    4. Click SDCC Linker and select Miscellaneous.
    5. Click the + icon under Other options, and enter "--model-large".
    6. Click OK to accept the change, then click Apply and OK on the project's Properties dialog box.
  • The c8051-elf-omf2elf command has a '-i directory' option to specify a directory to look in to automatically diagnose the correct combination of OMF and SDCC-generated CDB input files required to generate an ELF-format binary version of your program. This option will not accept a directory name if it has a trailing '/' character, like "-i ./". This will be fixed in a future release.
  • SoftConsole v2.1 uses a number of SDCC's options to disable most optimizations which cause problems with debugging. By default, SDCC compiles all optimizations; there is no flag dedicated to enabling or disabling them all as a group.
Quick Start Documentation
  • Please refer to the SoftConsole Quick Start Guide for an overview on getting started with SoftConsole. The July 2006 version of this document focuses on using earlier versions of SoftConsole and other tools to target CoreMP7, but the general approach still applies to SoftConsole v2.1 when targeting CoreMP7, Cortex-M1, or Core8051s with the qualifications that follow.
  • When creating a new project in SoftConsole v2.1 using the New Project wizard, you must select the appropriate project type on the Select a type of project page. In SoftConsole v1.x, only CoreMP7 was supported using the Embedded Executable (Gnu for arm-eabi) project type. In SoftConsole v2.1 you must choose one of the following:
    for CoreMP7: Embedded Executable (Actel CoreMP7 Target)
    for Cortex-M1: Embedded Executable (Actel Cortex-M1 Target)
    for Core8051s: Embedded Executable (Actel Core8051s Target)
  • The Quick Start Guide explains how to configure the FS2 In-Target System Analyzer for ARM Processor Cores (cliarm.exe) for CoreMP7 debugging as an External Tool named FlashPro3 On-Chip Debugging for CoreMP7 in Eclipse. The equivalent settings for the CodeSourcery ARM Debug Sprite for Cortex-M1 debugging are:
    Name (for example): FlashPro3 On-Chip Debugging for Cortex-M1
    Location: C:\Program Files\Actel\SoftConsole v2.1\
    Sourcery-G++\bin\arm-none-eabi-sprite.exe

    Working directory: C:\Program Files\Actel\SoftConsole v2.1\
    Sourcery-G++\bin

    Arguments: -m -l :3000 flashpro: coremp7-cm1
  • Likewise, configuration settings for the Actel C8051 Debug Sprite are:
    Name (for example): Actel C8051 Debug Sprite
    Location: C:\Program Files\Actel\SoftConsole v2.1\
    Sourcery-G++\bin\c8051-elf-sprite.exe

    Working directory: C:\Program Files\Actel\SoftConsole v2.1\
    Sourcery-G++\bin

    Arguments: -m -l :3000 flashpro: coremp7-c8051
  • While the Quick Start Guide explains how to configure processor debug support via External Tools, it is not explicit that you need to manually run the relevant tool before attempting to connect the debugger to a hardware target, for example:
    Run > External Tools > FlashPro3 On-Chip Debugging for CoreMP7
    Run > External Tools > FlashPro3 On-Chip Debugging for Cortex-M1
    Run > External Tools > Actel C8051 Debug Sprite
  • The Quick Start Guide outlines how to configure a SoftConsole project for on-chip debugging on hardware. However, starting with SoftConsole v2.1 users are no longer required to enter the initialization and run commands for debugging if the defaults are suitable:
    For a CoreMP7 target under the Commands tab, the Initialize commands text box will display:
    target remote :54545
    load
    tb main

    For a Cortex-M1 target, under the Commands tab, the Initialize commands text box will display:
    target remote :3000
    load

    For a Core8051s target, under the Commands tab , the Initialize commands text box will display:
    target remote :3000
    load

    For any of CoreMP7, Cortex-M1, or Core8051s, under the Commands tab, the Run commands text box will display:
    cont
  • For either CoreMP7 or Core8051s target, you can try debugging using the simulator. This is not yet supported, but is provided for users to experiment. (The simulator is not yet usable as a Cortex-M1 target.)

    By clicking the Commands tab, you can change the Initialize commands text box to have:
    target sim
    load
    Likewise, in the Run command text box, change it from "cont" to "run":
    run
  • To begin debugging:
    1. Make sure that the required debug support External Tool is running
    2. Click Debug to start a debug session
    3. If you removed "cont" or "run" command described above, in the debugger select
      Run > Resume, and it will run until the default breakpoint at main() is triggered.
Debug tools and desktop firewalls
  • Because the debug tools (In-Target System Analyzer for ARM® Processor Cores for CoreMP7 debugging, CodeSourcery ARM Debug Sprite for Cortex-M1 debugging, and Actel C8051 Debug Sprite for Core8051s debugging) communicate with GDB via a TCP/IP socket connection, any desktop firewall in use will need to be configured to allow such communication. Most desktop firewalls will alert you to the attempt and ask if you want to unblock/allow this communication. Unblock or allow the communication to proceed with debugging.
Managed Make project fails when running Kaspersky Anti-Virus/Internet Security
  • If you run Kaspersky Anti-Virus/Internet Security, you may find that Managed Make projects do not build. This happens when Kaspersky incorrectly identifies
    C:\Program Files\Actel\SoftConsole v2.1\Eclipse\plugins\
    org.eclipse.cdt.core.win32_3.1.1.200609270800\os\win32\x86\
    starter.exe
    as a threat to the system. To circumvent this problem, you will need to restore starter.exe if Kaspersky has quarantined it, and configure starter.exe as a Trusted Application (in Kaspersky: from the Settings menu, select Threats and exclusions > Trusted zone > Trusted applications).
CoreConsole project requirements for debugging
  • During debugging, SoftConsole communicates with the target Cortex-M1 or CoreMP7 processor through the FlashPro3 JTAG header via the FlashPro3 unit. To enable debugging through the FlashPro3 header, you must appropriately configure certain aspects of your design:
    • For Cortex-M1 debugging, the Cortex-M1 Debug Interface configurable option must be set to FlashPro3.
    • For CoreMP7 debugging, the CoreMP7Bridge Debug configurable option must be set to RealView or FlashPro3.
    • For Core8051s debugging, the Core8051s Include Debug block configurable option must be set to Yes.
  • You also need to connect the UJTAG interface of CoreMP7Bridge or Cortex-M1 to the top level of your design. This is achieved by connecting the UJTAG interface to the Top Level bar in CoreConsole, and subsequently routing this interface to the top-level module of the overall design, when the CoreConsole generated subsystem is instantiated as a component in a higher level module. For Core8051s, connect the DebugIF interface to the top level of your design. The DebugIF interface uses the same UJTAG connection as for the ARM processors, except that Core8051s does not explicitly use the string UJTAG in the signal names.
  • There is no need to apply pin assignments to the UJTAG signals as Actel's Designer tool will automatically recognize that the JTAG pins of the device are used for these signals.
Targeting software to hardware
  • When targeting a specific Cortex-M1/CoreMP7-based hardware platform, it is recomended to use an appropriate custom lD linker script and/or startup code (CRT0 etc.) tuned to the target. The default versions used in the absence of explicit custom versions may not work for a specific target platform, memory map, etc. For further information on the default CRT0 startup code and linker script see the files in C:\Program Files\Actel\
    SoftConsole v2.1\src and C:\Program Files\Actel\SoftConsole v2.1\Sourcery-G++\arm-none-eabi\lib\bare-ram.ld
  • Likewise, the default startup files for Core8051s are included with the SDCC compiler. The source files are located in C:\Program Files\Actel\SoftConsole v2.1\Sourcery-G++\lib\src\mcs51
FlashPro3 drivers
  • When you first plug the USB cable from the FlashPro3 into the PC (or plug the cable into a port you have not used before), the Found New Hardware Wizard opens, use the fp3b-cyusb.inf file if present (or fp3bload.inf if not) in the Libero IDE (e.g. C:\devtools\Libero_v8.0\FlashPro\Drivers) or FlashPro software (e.g. C:\devtools\FlashPro v6.0 SP1\Drivers) installation. Once the drivers have been installed, the USB cable should be plugged out and in again to ensure a reliable connection to the FlashPro3 for debugging.
  • In some cases after uninstalling SoftConsole v1.0, the required FlashPro3 driver will be removed and the relevant USB device will appear with a yellow warning/exclamation mark icon in Device Manager (in Windows: Start > Control Panel > System > Hardware > Device Manager > USB Controllers > FlashPro3 Programmer). To rectify this situation refer to the previous note.
  • Please refer to the FlashPro software documentation for more details about managing FlashPro3 device drivers.
Old SoftConsole project migration
  • In some cases, when opening projects created with previous versions of SoftConsole with SoftConsole v2.1, SoftConsole v2.1 will require some manual updating to correct tool paths (e.g. debug support External Tool paths etc.).
  • SoftConsole v2.0 beta users who have projects that they wish to convert/migrate for use with SoftConsole v2.1 should contact Actel for the utility required to do this.
Single stepping delays
  • In some situations single stepping (e.g. single stepping an empty for loop such as for (i = 0; i < 10000; i++) ; at the C code level) can lead to delays in debugger responsiveness without the possibility of breaking into the program from Eclipse/GDB (although this is possible using the FS2 In-Target System Analyzer for ARM Processor Cores console interface when debugging CoreMP7 programs).
  • If you find that debugger connectivity to the target is unreliable or not possible at all then one way to get back to a working setup is to:
    1. Power off the target hardware board
    2. Disconnect the FlashPro3 USB cable
    3. In Eclipse, terminate the GDB debugging session and the relevant debugger support External Tool
    4. If necessary, exit Eclipse altogether
    5. Power on the target hardware board
    6. Reconnect the FlashPro3 USB cable
    7. Run Eclipse and start a new debugging session

SDCC and Keil Compatibility Issues

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Many developers accustomed to the use of the Keil development tools for 8051 targets may not have had exposure to the free SDCC tools. SoftConsole uses SDCC for compiling and linking your Core8051s projects. As you develop your programs, or port your existing Keil-compatible code to use under SoftConsole for a Core8051s target, there are some fundamental differences you will want to keep in mind.

The SDCC compiler's User Manual (available under the Start menu entry for SoftConsole) covers such differences in detail. Some of the more important differences are highlighted here.

Syntax Differences
In your code developed with Keil, you can use
#pragma NOEXTEND
to make sure you've weeded out exactly what compiler-specific keywords exist.
SFR declarations
The Keil syntax with
sfr IOA = 0x80;
looks slightly different with SDCC, using either of
sfr at 0x80 IOA;
__sfr __at 0x80 IOA;
The SDCC "at" and "__at" keywords are used in place of an initialization-style statement. In the interests of pointing out possible compatibility issues, many users opt to choose the leading "__" version of these keywords to make their use more clear.

Also, SDCC does not require the bytes to be adjacent in memory for sfr or sfr16.

SBIT declarations
Also the case with SBIT, you use the "at" keyword. Instead of
sbit SEL = 0x86+0;
you should have one of
sbit at 0x86+0 SEL;
__sbit __at 0x86+0 SEL;
External Registers
Keil compilers looks for "_AT_" in the declaration of an external register, such as
EXTERN xdata volatile BYTE GPIO_LED_REG _AT_ 0xF200;
Instead, the SDCC style is
EXTERN xdata at 0xF200 volatile BYTE GPIO_LED_REG;
Printf Functionality

The SDCC compiler does support the use of printf(); however, you will need to create your own putc() function to implement the actual emitting of bytes to a specific device for stdout.

Macro Workarounds
Some users elect to take advantage of macro text substitution in their source code to make the creation of more compatible code less labour-intensive. For example, you can employ:
#define SFR(a,b) __sfr __at(a) b
#define SBIT(a,c) __sbit __at(a) c
#define SBIT(a,b,c) __sbit __at(a+b) c
#define SFR16(a,b) __sfr16 __at(((b+1)<<8) | b) a
This will enable you to use "SFR(0x80, IOA)" regardless of which specific syntax they're using.
Assembly Language Programming

If you are writing a program in assembly language rather than in C, you should be aware of some differences between the asx8051 assembler and Keil's A51. As noted by Daniel Clemente in his description of using SDCC with a particular development board:

  • Global symbols (tags accessible from outside) are specified with .globl (or with tag::). Then you don't need the -g when compiling.
  • Files are included with .include
  • Constants (equ) are done with NAME = value
  • You must use .area CSEG (CODE) before the code.
  • The hexadecimal values are written with 0xVALUE, and binary with 0bVALUE. In A51 they have the letter at the end.
  • You don't need the end instruction at the bottom of each file.
  • Keil ignores everything about upper/lower case, and even when in your code you're calling EZUSB_Delay1ms, for instance, at the assembler there's only defined the symbol EZUSB_DELAY1MS.
  • Symbols created by asx8051 must have the prefix _ (it means external symbol). sdcc adds it automatically when compiling C.
ISO/ANSI Compliance

There are some traits of the SDCC compiler that are not in full compliance with the ISO standard for the C programming language. Users who would like to know the specifics are encouraged to consult section 8.2, "ANSI-Compliance", in the SDCC User Manual (available in HTML and PDF format under the Start menu entry for SoftConsole).

Download and Install SoftConsole v2.1

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  • SoftConsole is available for FREE to download from the Actel website.
  • The SoftConsole Quick Start Guide is an excellent place to start getting an understanding of SoftConsole.

Download SoftConsole v2.1

  • Windows Version (110 MB)