Actel

What's New in this Release

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SmartFusion
SmartFusion MSS Upgrade Feature
  • Manages the upgrade from one MSS version to another
    • Maintains configuration and port names
    • Warnings are printed if any automatic replacement cannot be made
    • Available in right-click context menu in Libero Design Hierarchy
MSS Enhancements
  • An updated MSS version (2.1.108) is available from the Libero IDE Catalog Repository. Version 2.1.108 is required for all A2F200 and A2F500 designs.
  • Version 2.1.108 includes the following features:
    • MSS Watchdog Timer update
      • MSS v2.1.108 fixes a Watchdog Timer reset issue where an infinite loop will occur during the boot sequence if the Watchdog Timer is reset during the forbidden window.
      • Description of the issue:
        • The Watchdog Timer peripheral in the MSS can be configured to have forbidden and permitted timing windows that regulate when refreshing can be done. The size of the window is controlled by the value set in the WDOGMVRP control register. With MSS versions prior to MSS v2.1.108 (which includes System boot v2.2.100), an infinite loop during the boot sequence will occur if the Watchdog Timer is configured within the forbidden window and if the reset occurs due to refresh during the forbidden window. With MSS versions prior to MSS v2.1.108, the user could program a value greater than the load value in WDOGLOAD register or the maximum value (0xFFFFFFFF) to avoid being in the prohibited window so that the refreshing can be permitted any time within the load value.
      • Workaround/recommendation when using MSS versions prior to v2.1.108:
        • Avoid using the prohibited window by setting the maximum value which is also the reset value (0xFFFFFFFF)
    • Ethernet MAC signals are partitioned into two groups to clearly separate RMII management and data signals
      • RMII management signals
        • MDIO (MDI, MDO, MDEN) and MDC
      • RMII data signals
        • TXD0, TXD1, TX_EN, RXD0, RXD1, CRS_DV and RX_ER
      • Each group may be used either connected to MSS I/Os or connected to the fabric
      • The RMII management interface cannot be routed to the fabric in A2F200
      • The RMII data interface can be routed to the fabric in A2F200 and A2F500
    • Clock configuration circuitry configurator (MSS_CCC) enhancements
      • CLKB-GLB configuration is allowed if GLB is not used by FAB_CLK
      • The on-chip RC oscillator and main crystal oscillators outputs can be brought out to drive the fabric CCC input clocks (A2F500 only)
    • Embedded nonvolatile memory (eNVM) configurator (A2F500 only)
      • Two eNVM blocks are available and shown as a contiguous block of embedded flash memory (4096 pages) in the Cortex-M3 memory space. Note: The MSS configurator uses a certain number of user eNVM pages to store the MSS configuration. See the SmartDesign MSS Embedded Non Volatile Memory (eNVM) User Guide for more information.
      • The pages are located at the top of the eNVM address space.
      • Configurator View
        • There is one single configurator for both eNVM blocks.
        • Data storage and initialization clients can span the both eNVM blocks.
        • Visual display to:
          • Identify which eNVM block a client belongs to
          • Identify whether a client spans both blocks
      • One single EFC file is generated for programming
    • eNVM initialization client configurator now provides:
      •  A more intuitive 'destination address' entry
      • A pull-down list defining the possible targets (EMC, eSRAM and fabric) with actual Cortex-M3 memory mapped address ranges showing
    • Analog compute engine (ACE) configurator now includes:
      • Automatic round robin sequencing
      • Automatic sample rate computation
      • Analog comparator usability enhancements
        • You can configure inputs without having to first create services on those pads.
        • If a pad is used for another service, its user name is shown under the pull-down window.
      • Cortex-M3 interrupt mapping is shown in the Controller tab user interface Flag Registers list.
    • MSS renaming
      • Rename your MSS component
        • Available in right-click context menu in Libero Design Hierarchy
    • Auto promotion of MSS signals
      • All MSS signals are now automatically promoted when the user configures a signal to be used.
      • All tie offs and connectivity takes place in the top level SmartDesign component where the MSS is instantiated.
    • Firmware view enhancements
      • Includes a new download icon that indicates when a core needs to be downloaded before generation.
UPDATED  SmartFusion Fabric CCC (FAB_CCC) Configurator (for A2F500 Device*)
  • A Fusion-like clock conditioning circuit (CCC) configurator is available from the Libero IDE Catalog for instantiation into the SmartFusion fabric (A2F500 only)
    • One configurator addresses all options
      • Static and dynamic configuration
      • Glitch-less multiplexor
        • Between GLA and GLC
        • Between GLA and fabric
      • External Feedback
        • From dedicated FPGA I/O
        • From other logic on the fabric
      • Clock sources
        • From dedicated FPGA I/O (automatic instantiation of the I/O buffer)
        • From dedicated FPGA LVDS I/O (automatic instantiation of the I/O buffer)
        • From dedicated FPGA LVPECL I/O (automatic instantiation of the I/O buffer)
        • From other logic on the fabric
        • From on-chip RC oscillator
        • From main crystal oscillator
      • Instantiated as a separate component from the Libero IDE Catalog
    • *See #26782 in the Known Issues section below.

When configuring the FAB_CCC using the FAB_CCC configurator, users should not uses the following External Feedback options:

  • External IO
  • Fabric

These options will be removed in the next version of the FAB-CCC configurator.

SmartPower Enhancements for SmartFusion
  • Low power mode
    • Supports the VDDBAT rail for time-keeping mode
    • Static power results are updated.
  • MSS
    • Supports configuration dependent contributions for example if the ACE is disabled the MSS power is decreased by 10%.
    • Added eNVM static power data
  • Analog
    • Supports configuration-dependent, contributions-based number of ADC used, temperature monitor configuration, etc.
      • From 8 mW (oscillators only) to 55 mW (full configuration)
    • Updated the RC oscillator, main crystal and low power crystal contribution models
SmartFusion Programming
  • Programming file generation and programming for A2F500 devices
SmartFusion STD Speed Grade Support
  • STD speed grade has been redefined in the SmartFusion datasheet. Details are as follows:
Die Package Speed Core Voltage Temp Ranges
A2F200M3F 484 FBGA STD 1.5 V COM*, IND*
A2F200M3F 256 FBGA STD 1.5 V COM*, IND*
A2F500M3G 484 FBGA STD 1.5 V COM*, IND*
A2F500M3G 256 FBGA STD 1.5 V COM*, IND*
Temp Range MSS Speed Core (Fabric) Speed
*COM 80MHz 15% slower than A2F200-1 and A2F500-1
*IND 80MHz 15% slower than A2F200-1 and A2F500-1
IGLOO nano and ProASIC3 nano Timing and Power Updates

Timing and power models within SmartTime and SmartPower are now based on actual characterization of the silicon for the following devices.

  • IGLOO nano: AGLN010, AGLN015, AGLN020, AGLN250
  • ProASIC3 nano: A3PN010, A3PN015, A3PN020, A3PN250
IGLOO New Package Support
Die Package Speed Grade Core Voltage Temperature
AGLN125V2 81 CS STD 1.2, 1.5, 1.2 - 1.5 COM, IND
AGLN125V5 STD 1.5 COM, IND
AGLN125V2 100 VQFP STD 1.2, 1.5, 1.2 - 1.5 COM, IND
AGLN125V5 STD 1.5 COM, IND
Fusion Extended Temperature

An extended temperature selection (-55°C to 100°C) for Fusion devices is available. The selection is made in the Designer Device Selection dialog. Users must consult the datasheet for details on feature restrictions for operation below -40°C.

Die Package Designator Speed Grade Temperature (-55°C to 100°C)
AFS600 256 FBGA K STD, -1 EXT
484 FBGA K STD, -1 EXT
AFS1500 256 FBGA K STD, -1 EXT
484 FBGA K STD, -1 EXT
Axcelerator

The following package is added for RTAX2000D:

Die Package Speed Grade Temperature
RTAX2000D 352 CQFP STD STD, MIL

Additional Axcelerator features:

  • Place-and-Route
    • Rebuffer of unordered buffer trees to cascaded math blocks for RTAX2000D and RTAX4000D devices. Rebuffering is a specific RTAX-DSP performance improvement for medium to high fanout nets driving math blocks even through buffer trees.
    • For AX, RTAX-S, and RTAX-DSP devices, the repair min-delay violations option has been improved for robustness of incremental routing
  • The MultiView Navigator now displays all nets originating from MATH and RAM blocks
  • RTAX4000D programming file generation is available in Designer for use with the Silicon Sculptor programmer. Silicon Sculptor software v5.6.0 and the SMAX-352CQ4K-ACTEL programming module support programming for the RTAX4000D.
  • Simulation support for GCLR/GPSET. During power up of Axcelerator devices, all the sequential elements in the FPGA fabric are set to '0' or '1' through a Global SET/CLR fuse. A user can choose the SET/CLR option while generating the programming file. Each sequential element in the fabric has two additional controls GCLR/GPSET which are active only during power up. After power up GCLR/GPSET inputs are pulled high and user inputs are active. Since GPSET and GCLR are not user inputs, CAE macros do not have these inputs. Libero IDE v9.0 SP1 adds simulation support for the power up behavior of sequential elements. Two additional precompiled libraries and one source file are provided for the Axcelerator family. In total there are three precompiled libraries for Verilog flow and three precompiled libraries for VHDL flow. All libraries are installed during the Libero IDE installation when the Axcelerator family is selected and located at <installation>/Designer/lib/modelsim/precompiled. Read the Antifuse Macro Library Guide for more information.
FlashPro

FlashPro includes the following new features:

  • A2F500 programming
  • SVF and IEEE 1532 support added for SmartFusion
    • Note: IEEE 1532 programming files can only be exported in FlashPro when a fabric database (FDB) file has been imported (25219).
  • Windows 7 operating system qualified (Professional version)
  • Vista and Windows 7 x64 (64-bit) USB driver support added for FlashPro3 and FlashPro4 programmers
  • Driver support for PCMCIA-to-Parallel port converter cards such as the StarTech CB1PECP or Quatech SPP100 for use with Actel FlashPro and FlashPro Lite parallel port programmers.
Operating System Support

Windows 7 Professional Version. Libero IDE tools are now fully tested and qualified on Microsoft Windows 7 Professional edition. Libero IDE software may function on other Windows 7 versions, however Libero IDE is only tested on Windows 7 Professional edition.

RedHat Enterprise Linux. Libero IDE tools (not including FlashPro and SoftConsole) are fully tested and qualified on RedHat Enterprise Linux RHEL 4.0, RHEL5.0 and RHEL 5.2. Libero IDE software may function on other Linux versions, however Libero IDE is only tested on RedHat Enterprise Linux RHEL 4.0, RHEL 5.0 and RHEL 5.2.

See System Requirements for complete details.

ProASICPLUS

This service pack includes enhanced layout algorithms for ProASICPLUS (APA) devices, which can improve margin in the presence of overstress. Actel recommends that you always operate ProASICPLUS devices within the voltage conditions specified and use this latest release of Libero IDE software when designing Actel ProASICPLUS devices.

New Known Limitations, Issues and Workarounds

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SmartFusion Design Flow

UPDATED  26782 - No design rule check to prevent use of FAB_CCC PLL in A2F500 FG256 package
The PLL within the FAB_CCC of the A2F500 device in the 256 FBGA package is not and will not be available. The FAB_CCC PLL is only available in the A2F500 484 FBGA package. Although the FAB_CCC without the PLL may be useful in some applications, in Libero 9.0 SP1 there is no design rule check that prevents the user from instantiating the FAB_CCC PLL into a SmartDesign project, nor is there any design rule check at Designer Compile to prevent an attempted place and route. The FAB_CCC PLL is not bonded out to a pin in the 256 FBGA package so layout will not be complete.

Workaround: You must select the 484 FBGA package when instantiating the FAB_CCC and using the PLL within it.

In the next software release, a design rule check will be put in place to prevent instantiation of the FAB_CCC in the A2F500 256 FBGA package.

SmartFusion MSS

26100 - ACLK is not set by default when opening ACE.
On a brand new MSS design, the user should open CCC configurator first and click OK before entering the ACE configurator. Otherwise, the ACE configurator sample rate calculation will display 0.

26454 - For ABPS with +/- 15.36 gain, threshold above 15.356 is not interpreted correctly.
Threshold values of 15.357, 15.358, and 15.359 are interpreted as 0. Customer should use 15.356 if they want to have the maximum value.

SmartPower

26277 - Vectorless power estimation fails in the presence of multi-tile flip-flops.

Workaround: Uncheck the vectorless feature and use fixed value toggle rate.

FlashPro On-Chip Debug

25969 - On-chip debug is not supported SmartFusion A2F500.
On-chip debug for SmartFusion A2F500 will be available in a future release.

FlashPro

UPDATED  27175 - FlashPro fails to import .mem files that are larger than 256K for A2F500.

Workaround: Import a .mem file larger than 256K with the SmartFusion MSS Configurator, then generate an EFC file by generating the MSS. Then import the EFC file into FlashPro. Some warnings may appear, which can be ignored. .mem files can be any type of .mem file ie Intel Hex, Motorola, etc.

26564 - SmartFusion STAPL files have syntax errors with Actel STAPL player.
A2F500 STP files have syntax errors on Actel STAPL player. A2F200 STP file has syntax errors on Actel STAPL player when executing ACTION DEVICE_INFO. This issue will be fixed in a future release.

Workaround: Use a PDB to export a chain SVF/STAPL for SmartFusion.

Software Fixes in v9.0 SP1

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Customers should refer to their respective Technical Support hotline case number. If a Software Action Request (SAR) was created for the case and it has been fixed in this Libero IDE release, the SAR and associated case number will be on the list below.

SAR Case
17346 1-35050850
25713 1-40649516
24822 1-40018885
14879 1-34820731
24202 1-39379257
24589 1-39697331
24712 1-39829797, 1-39887438
21735 1-37930341
23672 1-39205536
24996 1-39986319
20920 1-37471261
21023 1-37659882
24265 N/A

Download Libero IDE v9.0 SP1

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The version of software that you requested is no longer the most current version available. Please download the most recent software update.

  • Windows Version - 9.0.2.9

If you need this specific version of software, please contact Actel Tech Support:
Email: tech@actel.com
Phone: 1.800.262.1060