Libero IDE v8.6 Release Notes
(updated on Nov 30, 2009)
Thank you for your interest in Actel's Libero Integrated Design Environment
(IDE) v8.6.
Post-Layout Probe Insertion
Probe insertion is a post-layout process that enables an IGLOO, ProASIC3, or Fusion designer to insert probes into the design and bring signals out to package pins on the device to evaluate and debug the design. Probe insertion has a minimal timing effect on the overall design and is a convenient way to quickly understand logic issues in any design. While testing a programmed device, the user's design may have inherent logic errors due to inadequate simulation test coverage, or external signals arrived out of sequence, or timing setup and hold violations were ignored.
Probe insertion enables selection of internal nets anywhere in the design, connection of signals to unused pins, and running of incremental layout. Nets are selected and assigned probes using the "Generate Probed Design" feature available from the Designer Tools menu. If all package pins are already assigned, a used pin can be temporarily disconnected to enable connection of the probed signal to that pin. The re-routed design can then be programmed into the FPGA, where an external logic analyzer or oscilloscope can be used to view the probed signal. The package pins and port names are reported in Designer's log file. Once the evaluation is complete, the original saved layout file can be used if no design modifications are needed, or any necessary modifications can be made to the design so that layout can be run again. Post-layout probe insertion is faster than using Synplicity Identify Actel Edition (AE), which requires instrumentation of the design at the RTL level and running synthesis.
Note: The pre-optimized netlist view in the MultiView Navigator (MVN) shows the inserted probe floating and not driven by any net. The pre-optimized netlist is the original user netlist, and the probe insertion does not modify user netlists. The post-optimized netlist view in MVN does show the probe driven by the probed net. This is the current expected behavior.
SmartPower
A new analysis algorithm provides a quick and accurate method for performing power analysis without having to utilize the traditional Value Change Dump (VCD) file. In the absence of simulation data from which a VCD file is generated, this feature provides better activity estimation than the traditional default toggle rate method. This new vectorless methodology improves the power analysis results typically to within +/- 10% of that achieved with a VCD file driven analysis, but requires a substantially shorter runtime, and the designer does not have to create test vectors and capture simulations. The designer can still 1) define specific frequencies (toggle rates) on individual nets or a class of nets (like asynchronous clear/preset), 2) initialize activities from timing constraints, 3) import a partial VCD, or 4) mix and match any of the above. Vectorless Estimation is used by default in SmartPower for new designs. Designs that already have committed SmartPower settings will use the saved settings. For the most accurate power report Actel recommends use of a simulation driven VCD file.
An "I/O Advisor" analyzes Output Load, Drive Strength, and Slew Rate settings in a design, and provides an opportunity for the designer to select alternative settings to reduce the power consumption of I/Os. For Drive Strength and Slew Rates, alternate suggested values are shown, if improvements in power consumption or timing slacks are possible. The I/O Advisor analyzes power based on existing timing constraints, and identifies both positive and negative timing slacks. Adjustments can be made to improve negative slacks and/or balance slacks in the interest of lowering power consumption. The I/O Advisor provides an opportunity to input "what-if" values for Output Load, Drive Strength, and Slew Rate to understand in real time their impact on the I/O timing and power.
The Summary tab now includes a grid that displays design activity coverage and the annotation methodology for each category of pins (clocks, registers, combinational, etc.). The grid provides a comprehensive view of activity coverage of the design. Based on coverage values, the designer may choose to improve the quality of coverage by modifying the methodology within SmartPower, such as using a VCD file, Vectorless Estimation, or Fixed Frequency.
Static current for IGLOO devices is now updated to reflect worst-case scenario.
Firmware Catalog
The Firmware Catalog is a standalone executable program that supports SoftConsole, Keil Software, or IAR Systems embedded processor development systems, for the purpose of locating and generating firmware that is compatible with FPGA designs used in Libero IDE. Software DirectCore IP drivers and a Hardware Abstraction Layer (HAL) is available for Actel's Cortex-M1, CoreMP7, and 8051s processors that can be downloaded directly into SoftConsole, Keil Software, or IAR Systems development systems. The Firmware Catalog is installed automatically when Libero IDE v8.6 installs. Non-Libero IDE users can download the Firmware Catalog separately.
SmartDesign
The SmartDesign Canvas now provides complete access to previously hidden internal bus interface pins of a core. This is useful when the designer needs to connect a peripheral to a non-standard bus or custom protocol. In addition, when a bus is sliced, all sliced pins can be promoted to top level. When a bus is instantiated, the slot number visibility on the bus is improved. When the SmartDesign Canvas is crowded and instances are overlapping, instances can be selected and brought to the top of the Canvas to expose all pins and routing.
SmartTime
The IGLOO PLUS timing models in SmartTime are now based on characterized silicon.
5 V-Tolerant I/Os for RTAX-S/SL
5 volt tolerance has been added to outputs of 3.3 volt LVTTL I/Os for RTAX-S/SL devices. Using Libero IDE v8.6, outputs as well as inputs for 3.3 volt LVTTL I/Os include an option to enable a 5 volt clamp.
Designer STAPL Generation
STAPL file enhancements deliver faster programming for gang programming on Silicon Sculptor 3 and Silicon Sculptor II programmers, as well as the BP Microsystems auto programmer. With this new STAPL file, the programming time for multiple parallel devices nearly matches the programming time of a single device.
FlashPro v8.6
In FlashPro, I/O settings for used and unused I/Os when using a PDB programming file can be specified during programming. The I/O settings during programming can be set to drive high, drive low, tri-state, or to the last known state in normal view. For further customization, the Boundary Scan Register (BSRs) for each I/O can be modified to allow for more detailed customization of the I/O states during programming. These settings can now be saved and loaded into a file.
FlashPro now includes database support for non-Actel devices. A BSDL or group of BSDL files for non-Actel devices can be imported into FlashPro, which then supports automatic device identification of Actel and non-Actel devices, and construction of a chain.
FlashPro also supports placing unselected Actel IGLOO, ProASIC3, Fusion, and ProASICPLUS devices in a daisy chain into a high impedance during daisy chain programming.
A FlashPro3x programmer setting in the FlashPro programming software has been added to switch between free running clock and discrete clocking TCK mode.
Read the FlashPro v8.6 release notes for complete details of the release.
SoftConsole v2.3
SoftConsole v2.3 addresses issues discovered in v2.2. SoftConsole v2.3 is available on the Libero IDE v8.6 DVD or as a standalone download.
Read the SoftConsole v2.3 release notes for complete details of the release.
Fusion Absolute Addressing Option Added for NVM Clients
In relative addressing, the addresses in the memory content file are relative to the client. The user specifies the location of the client by entering the start address. This becomes the address 0 from the memory content file perspective and the client is populated accordingly. For example, if a client is specified with a start address of 0x80 and the content of the first byte of data in the memory file is 01, then 01 is written to location 0x80.
In absolute addressing (available in the Initialization Client and the Data Storage Client), the memory content file dictates where the client is placed in the flash memory block. The address in the memory content file for the client becomes absolute to the whole flash memory block. When the absolute addressing option is enabled, the software extracts the smallest address from the memory content file and uses that address as the start address for the client.
New Device Packages, Device Support, and Device Changes
New Device Packages
| Device |
Package |
Speed Grade |
Temperature |
| RTAX4000D |
352 CQFP |
STD |
Mil |
New Device Support
| Device |
Package |
Speed Grade |
Temperature |
| A3P250 |
132 QN |
STD, -1 |
T (Grade 1): -40°C to +135°C
T (Grade 2): -40°C to +115°C |
Device Name Changes
| FROM |
TO |
| RTAX2000D CCGA/LGA |
RTAX2000D CCGA/LGA DSP |
| RTAX4000D CCGA/LGA |
RTAX4000D CCGA/LGA DSP |
Programming File Generation
Programming File Generation is added for the following devices:
- AGLN250
- M1A3P400
- M1A3PE3000L
- Synplicity Synplify/Synplify Pro Actel Edition (AE) 2009.03A-2
This version adds inference for DSP 18x18 Multiply, Multiply-add, and Multiply-subtractor math blocks for Actel's RTAX-DSP devices.
- Mentor Graphics ModelSim AE 6.5a
- SynaptiCAD WaveFormer Lite 12.30a*
- Actel ViewDraw 7.7.0
- Actel FlashPro v8.6
- CoreConsole v1.4
- SoftConsole v2.3
- Firmware Catalog v8.6
- Actel Silicon Explorer v5.2
- Synplicity Synplify DSP AE 2009.03a
- Synplicity Identify AE 2009.03a SP1
- Mentor Graphics Precision RTL AE Synthesis 2009a
* Effective December 1, 2009, SynaptiCAD WaveFormer Lite will no longer be available from Actel, and new licenses will no longer be generated. For more information, read the related WaveFormer Lite article.
- Synplicity Synplify/Synplify Pro AE 2009.03A-2
This version adds inference for DSP 18x18 Multiply, Multiply-add, and Multiply-subtractor math blocks for Actel's RTAX-DSP devices.
- Mentor Graphics ModelSim AE 6.5a
- Actel ViewDraw 7.7.0
- Actel FlashPro v8.6
- Actel Firmware Catalog v8.6
Note Effective December 1, 2009, SynaptiCAD WaveFormer Lite will no longer be packaged in the Libero IDE v8.6 download; and new licenses will no longer be generated. For more information, read the related WaveFormer Lite article.
The software tools below are not part of the Libero IDE v8.6 download. However, they are available as standalone downloads. Release notes and other information are also available.
The following software tools do not need to be downloaded if the Libero IDE v8.6 is installed from the DVD:
Libero IDE v8.6 is supported on Windows Vista Business, Windows XP Pro, and Red Hat Linux 4.0 and 5.2.
For more information, view the complete System Requirements.
Libero IDE v8.6 requires a current Libero IDE v8.0 license. Register for a free Libero IDE Evaluation or Gold license, or contact your local Actel Sales office to purchase a Libero IDE Platinum license.
Unless otherwise noted, these issues apply to all devices.
WaveFormer Lite
Effective December 1, 2009, SynaptiCAD WaveFormer Lite test bench generation software will no longer be available as part of the Libero IDE software toolset. If you had an unexpired Libero Gold or Libero Platinum license as of October 6, 2009, your license was regenerated and resent to include a permanent feature line which allows the current version of WaveFormer Lite (12.30a) to work indefinitely. If you received a new Libero Gold or Libero Platinum license since October 6, 2009, your license includes the permanent feature line which allows the current version of WaveFormer Lite (12.30a) to work indefinitely.
Libero IDE v8.6 including WaveFormer Lite 12.30a will continue to work when used with the licenses noted above. Previous versions of Libero IDE and WaveFormer Lite will work with those licenses as well.
Customers that need a dedicated test bench generation tool can consider SynaptiCad's WaveFormer Pro software. Please contact SynaptiCad for information on WaveFormer Pro. Profiles can be set up within Libero IDE Project Manager in the same manner as they are set up for WaveFormer Lite.
Alternatively, many users create their own test benches. Ample information is available on the internet regarding the creation of HDL testbenches.
HDL Text Editor
19963/19932: Uncomment and highlighting of text doesn't work in Libero IDE HDL editor
For both VHDL and Verilog, you can comment out text in the Libero IDE text editor by highlighting the text and right-clicking Comment out. However, if you highlight the same text and right-click Uncomment out, it does not work. Also, commented out text color should change to green, rather than black like the rest of the code.
ModelSim/Simulation
20429 – ModelSim Wave window viewing bug in 6.5a (Libero IDE v8.6)
When using the Wave window in version ModelSim 6.5a, you may see "disconnected" scrolling between signal name list and waveforms and experience the inability to select signals or add signals to the signal name list.
Workaround: Click View > Refresh Display to restore normal operation. Alternatively, you can re-run the simulation.
SmartDesign
18730 - Top-level ports connected to an instance are not deleted when the instance is deleted from SmartDesign
When an instance is deleted in SmartDesign, the top-level ports connected to this instance are not automatically deleted. You must manually delete these top-level ports to prevent connectivity errors in the design.
18947 – SmartDesign Canvas Instance Placement is lost for Libero IDE Linux designs converted from a previous version
In the Linux release of Libero v8.6, projects converted from a previous Libero IDE release will lose their SmartDesign Component's Canvas Instance Placement.
Workaround: Run the Auto-Arrange tool by selecting the Canvas menu and choosing Auto-Arrange Instances and Auto-Arrange Connections.
Synplify Pro
18736 – Default location and name of Identify implementation are changed in Synplify/Pro vC-2009.03A
SmartPower
18975 - Limited number of custom power modes available
In SmartPower v8.6, the number of Active-Mode-based custom power modes is limited to 5 modes. If you try to create more than 5 Active-based Custom Power Modes, an error dialog window is displayed which states:
The maximum number of Active-based custom modes has been reached. You need to delete an existing Active-based custom mode before creating a new one.
Designer Post Layout Probe Insertion
18857 - Inserted probe is not shown as connected in original netlist view in MultiView Navigator (MVN)
The inserted probe is not shown as connected to anything in original netlist view in MVN. It is shown correctly connected in the optimized netlist view.
Designer Compile: RTAX-DSP
15036 - Compile is invalidated on pre-v8.6 designs
Compile will be invalidated on any RTAX2000D or RTAX4000D designs that were created prior to the v8.6 release due to an update in the data library. You will see the following messages when opening an existing design with Libero IDE/Designer v8.6:
Warning: The design uses outdated library data. Invalidating Compile. Compile must be re-run.
You can preserve your existing Layout by running the placer with Incremental Mode "FIX" and the router with Incremental Mode "ON".
Designer I/O Settings
18128 – Invalid I/O Settings specified by the user are not caught by Designer when using TCL flow
In Designer v8.6, the settings for the I/O State During Programming can be exported into a IOS file and loaded into the FlashPoint Programming File Generation wizard in Designer or FlashPro. The valid I/O states during programming are '1', '0', or 'S', and invalid values are caught when importing the IOS file via the FlashPoint GUI. However, in the TCL Scripted Flow, if the I/O State During Programming is set to an invalid value either in a user-modified IOS file or directly via a TCL –set_io_state command, Designer does not report the error, and a programming file is not generated.
Workaround: Use the FlashPoint GUI to set the I/O State During Programming. A valid IOS file can be exported as necessary, and you must ensure that you do not manually modify the IOS file with invalid states.
RTAX-DSP Core Configurators
18805 – The minimum version of Libero IDE that DSP configurators can be used with is v8.5 SP1 (RTAX2000D, RTAX4000D)
The DSP cores for RTAX-DSP devices, SgHardMult, SgHardMultAddSub, and SgHardMultAcc, must be used with Libero IDE v8.5 SP1 or a later release. These cores are available in the Actel IP repository ready to be downloaded into a local vault.
FlashPro Programming Software
Refer to the FlashPro v8.6 release notes.
Customers should refer to their respective Techinal Support Hotline case number. If a Software Action Request (SAR) was created for the case and it has been fixed in this Libero IDE release, the number will be on the list below.
- 5009
- 5661
- 5697
- 6716
- 9752
- 9930
- 10456
- 10497
- 10675
- 10815
- 12499
- 12681
- 12779
- 13243
- 13251
- 13313
- 13395
- 13529
- 13613
- 13752
- 13801
- 13962
- 14228
- 14311
- 14395
- 14642
- 14952
- 15001
- 17256
- 17344
- 17782
- 18147
- 18444
- 18446
Choose one of the following, depending on your system's operating system - Capture 8.6.0.34:
