Libero IDE v8.5 Service Pack 1 (SP1) Release Notes
(Feb 23, 2009)
Thank you for your interest in Actel's Libero Integrated Design Environment (IDE) v8.5 Service Pack 1.
What's New in this Service Pack
Important Information for AX/RTAX-S Users
Programming File Generation
There is no reliability issue with devices which have successfully passed programming.
If the "Use the global set fuse" option in Designer's Generate Programming File dialog is not used (unchecked), no action is required.
If the "Use the global set fuse" option is selected, and devices were programmed successfully, no action is required.
If the "Use the global set fuse" option is selected AND you have experienced programming failures, you must install this release and regenerate your programming file. This release includes a fix for AX and RTAX-S programming (*.afm) file generation to eliminate a programming failure that sometimes occurs, if the "Use the global set fuse" option is selected.
Simulation Libraries
The following problem is resident in all software releases prior to v8.5 SP1.
If you inadvertently generate an undesired RAM configuration for AX/RTAX-S where the depth parameter is not a power of 2 (2, 4, 8, 16, 32,...), the simulation library does not detect any out-of-range memory access.
For example, if you intended to create a 480x32 RAM and inadvertently generate (using SmartGen) or manually configure a 384x32 RAM, simulation of the RAM using the test bench created for a 480x32 RAM does not report any problem when you read or write from/to the non-existent memory space (from 384 to 479). A programmed device however will reveal this problem in the FPGA since this will cause a memory functional failure.
This problem is now fixed in the simulation library. You will get a warning message as below, and for memory read, the read data will be shown as unknown:
<Write/read> address is out of range. <Waddr/Raddr> = <driven value>, Max write address = <max allowed value>
Important information for AGL060, AGLP060, and AGLN250Z users
The following CS packages no longer support instantiation of a Phase-Locked Loop (PLL):
| IGLOO |
IGLOO PLUS |
IGLOO nano |
| AGL060V2-CS121 |
AGLP060V2-CS201 |
AGLN250V2Z-CS81 |
| AGL060V5-CS121 |
AGLP060V5-CS201 |
AGLN250V5Z-CS81 |
Release v8.5 SP1 will identify designs with PLL during compile. If a PLL is detected a warning message will instruct you to change to another package, or remove the PLL to continue with the current package. Designs that have completed layout will be invalidated and a recompile is required. Contact your Actel FAE if you have questions.
Post-Silicon Characterized Timing for RTAX4000S
The timing models in SmartTime are now based on actual silicon characterization.
-1 Speed Grade for RTAX4000S
This service pack introduces a -1 speed grade for the RTAX4000S. A -1 speed grade is 10% faster than the Standard (Std.) speed grade.
SmartTime Enhanced Min Delay for RTAX4000S
SmartTime now provides conservative minimum delay/hold-time analysis based on RTAX4000S characterized silicon timing data. This new feature eliminates the need to over guard-band a design for minimum delay, providing a more comprehensive, precise way to perform chip-to-chip evaluation of external setup/hold and clock-to-out timing.
Programmable Input Delay for RTAX-S
Input delay options (per I/O bank) are now available for all RTAX-S devices. To set the input delay value for an I/O bank:
- Select the I/O bank in either ChipPlanner or PinEditor.
- From the Edit menu, choose "I/O Bank Settings", and then click "More Attributes".
- Drag the slider bar to the desired value. The delay is bank specific.
Repair Min Delay Violations for RTAX-S
The Advanced Layout option for repair of minimum delay violations for RTAX-S devices has been enhanced to take advantage of programmable delays on I/O input buffers. The feature inserts delay in paths where the minimum delay is not being met, while simultaneously checking maximum delays to ensure no violations are being introduced.
Performance Improvement for RTAX-S Designs Containing RAM
Layout improvements for all AX and RTAX-S designs containing RAM can realize an average of 5% additional performance improvement when higher effort levels (4 and 5) are used in the Designer Layout Options. RTAX4000S performance can improve 15% on average. To achieve the higher performance, the runtime may increase as much as 60% when using effort levels 4 and 5.
Routing Regions for ProASIC3, IGLOO and Fusion
A new Routing option has been added to the Region Properties dialog box in the ChipPlanner tool for ProASIC3, IGLOO and Fusion families. To access this dialog, right-click on a region in the Regions tab of the Hierarchy window, and choose "Properties". Selecting the Constrain routing option specifies that routing will be constrained, in addition to the placement. It is further influenced by the Region type selection.
| Region type |
Conditions |
| Inclusive |
An Inclusive Routing Region is an Inclusive Placement Region (rectilinear area with assigned macros) along with the following additional constraints:
- For all nets, internal to the region (the source and all destination pins belong to the region), routing must be inside the region. In other words, such nets cannot be assigned any routing resource which is outside the region or crosses the region boundaries.
- Other nets not internal to the region can be assigned routing resources within the region.
|
| Exclusive |
An Exclusive Routing Region is an Exclusive Placement Region (rectilinear area with assigned macros) along with the following additional constraints:
- For all nets, internal to the region, routing must be inside the region. In other words, such nets cannot be assigned any routing resource which is outside the region or crosses the region boundaries.
- For any net, which does not have pins inside the region, it cannot be assigned any routing resource, which is inside the region or crosses any region boundaries. Local clocks and globals are excluded, as are interface nets, since interface nets do cross the region boundaries.
|
| Empty |
No routing is allowed inside the region. Local clocks and globals are excluded and can cross the region boundaries. |
When Constrain routing is selected, an additional option to Over-constrain placement for routability becomes available. This usually creates a tighter placement region, e.g. a normal MxN Inclusive placement region would be shrunk to (M-2)x(N-2). On the other hand, the prohibited region for external nets in case of Exclusive and Empty Region types would usually expand to (M+2)x(N+2).
These options have also been added to the define_ region PDC command.
| Region Properties dialog box option |
Corresponding PDC define_region option |
| Constrain routing |
-route yes/no |
| Over-constrain placement for routability |
-push_place yes/no
|
SmartDesign Enhancements
You can now access all pins inside of a bus interface to make independent connections as needed.
Bus slices can now be promoted to Top level.
DatGen File Generation
DirectC users can now generate programming data files from Designer software. DatGen from previous DirectC versions can continue to be used to generate .dat files for the corresponding DirectC version.
CoreEDAC Use with Libero IDE
The recently released DirectCore CoreEDAC can be downloaded and used with Libero IDE v8.5 SP1. When the Catalog displays "New Cores Available", just click to view Actel's web repository and select the cores of interest to download. CoreEDAC cannot be used with Libero IDE versions older than v8.5.
IGLOO Package Additions
| IGLOO |
Package |
Speed Grade |
Temperature Range |
| AGL020V2 |
81 CS, 81 UC |
STD |
COM, IND |
| AGL020V5 |
| AGLN250V2Z |
81 CS |
STD |
COM, IND |
| AGLN250V5Z |
Package Change for RTAX2000D
The RTAX2000D device is being shifted from the 1152 CCGA/LGA package to the 1272 CCGA/LGA package to be more compatible with the RTAX4000D.
Programming File Generation
Programming File Generation is added for:
Libero IDE/Designer now qualified on Windows XP SP3
Libero IDE v8.5 and v8.5 SP1 is fully tested on Windows XP SP3.
FlashPro v8.5 SP1
FlashPro v8.5 SP1 is included in Libero IDE v8.5 SP1. Read the FlashPro v8.5 SP1 release notes for latest features and details.
Known Issues and Workarounds
5652 - LVCMOS12 output drive needs to be set through PDC or MVN.
LVCMOS12 I/Os with a default output drive of 1 mA are supported in the dies specified and required macros (LVCMOS12 output, tri-state and bidirectional buffers with 1 mA output drive) are not available in the CAE libraries. Users need to set this output drive explicitly through one of the following methods during Designer layout:
- PDC file
- MVN I/O Attribute Editor
The above flow needs to be used until the required macros are available in the libraries.
Affected devices:
- ProASIC3: A3P030, A3P015, A3PN010, A3PN015, A3PN020
- IGLOO: AGL030V2/V5, AGL015V2/V5, AGLN010V2/V5, AGLN015V2/V5, AGLN020V2/V5
- Fusion: AFS090, AFS250
Cases and SARs Fixed in this Release
| SAR Number |
Tool |
Case Number |
Symptom |
| 13801 |
Designer |
1-34350511 |
Crash while changing the package |
| 10160 |
SmartDesign |
|
AV pin disconnected on startup |
| 9463 |
SmartDesign |
|
Individual Interface signals are not transparent |
| 10150 |
SmartDesign |
|
All connections disappeared — Unable to remove fixed connections |
| 78130 |
Designer |
|
Need to update spec document for SVF headers |
| 12732 |
SmartDesign |
|
VHDL generated has syntax errors for VHDL library |
| 12779 |
SmartDesign |
1-33488250 |
Project Converted from 8.4 crashes with SmartHeap on open |
| 12499 |
SmartDesign |
1-33227501 |
Assertion in Viewmgr::ViewManager:: CloseAllDesignDocs |
| 12281 |
Designer |
|
Layout crashes during multipass while generating Power report |
| 13465 |
IP Framework |
|
Generic map is missing for PCIF in SXA |
| 10692 |
Macro Library |
|
CorePCIF simulation fails in Libero v8.4 simulation library |
| 9752 |
Designer |
1-32826861 |
M1A3P1000 Layout Fails in v8.4 |
| 9443 |
Designer |
|
M1A3P250 designs are failing at layout |
| 13529 |
SmartGen |
1-32718346 |
SmartGen Sync Load Counter Erroneous Output |
| 13613 |
Simulation Libraries |
|
A simulation library problem for AX/RTAX-S |
Download Libero IDE v8.5 SP1
The version of software that you requested is no longer the most current version available. Please download the most recent software update.
- Windows Version - Capture 8.5.1.13
- Linux Version - Capture 8.5.1.13
If you need this specific version of software, please contact Actel Tech Support:
Email: tech@actel.com
Phone: 1.800.262.1060
