Libero IDE v8.5 Release Notes
(updated on Jul 21, 2009)
Thank you for your interest in Actel's Libero Integrated Design Environment
(IDE) v8.5.
Project Manager, SmartDesign, and Core Catalog available with Designer License
Traditional "Designer Only" users now have access to "Libero Standalone (SA)" which is Libero IDE without the front-end OEM tools Synplify/Pro AE, ModelSim AE, and WaveFormer Lite. This provides Designer users the Project Manager features including SmartDesign and the Catalog, which includes DirectCores, SmartGen cores, and Actel macro cells. Designer license holders can now create simple or complex processor and bus-based SoC designs using SmartDesign and its rich library of Actel-generated functional cores, plus their own HDL modules. Libero SA works with existing Designer licenses. Select the "Install Libero Standalone" from the main installation window.
Axcelerator RTAX-DSP
Libero IDE v8.5 provides design flow for Actel's new radiation-tolerant DSP-equipped Axcelerator RTAX2000D and RTAX4000D FPGAs, including a new 18-bit by 18-bit math block capable of operating at 125 MHz. Configuration and implementation of up to 120 radiation-tolerant math blocks can be managed, for a total throughput of 15 billion multiply/accumulates per second (15 GMACS). The 18X18 math block is available in the Libero IDE Catalog Macro Cell library. It can easily be implemented into SmartDesign or User HDL, and managed through Libero IDE's standard synthesis, simulation, and layout flows. The embedded radiation-tolerant DSP math block supports simple signed 18x18 multiply, dual signed 9x9 multiply, multiply plus accumulate, plus cascaded multiply applications, enabling efficient implementation of DSP structures, such as finite impulse response (FIR) and infinite impulse response (IIR) digital filters, fast Fourier transforms (FFT), inverse Fourier transforms (IFT), discrete cosine transforms (DCT), correlators, and digital IF up/down converters. See the Antifuse Macro Library Guide for a full description of the RTAX-DSP macro.
Wide Operating Range I/Os for IGLOO, IGLOO PLUS v2, and ProASIC3L Devices
In v8.4, Libero IDE introduced a "wide operating range" 1.14 to 1.575 volts core voltage (VCCA) for the v2 (1.2 V) IGLOO, IGLOO PLUS, and ProASIC3L devices, enabling the core to be operated anywhere within the 1.14 to 1.575 volt range, or in battery applications where the voltage will decay below 1.5 volts.
Libero IDE v8.5 allows you to address applications where the entire FPGA, including I/Os, can be operated at any point within the range of 1.14 to 1.575 volts, or operated from a single 1.5 volt battery that decays over time. New "wide range" LVCMOS 1.2 volt and LVCMOS 3.3 volt I/Os powered by VCCI have been added to the I/O technology options that support 1.14 to 1.575 and 2.7 to 3.6 volts, respectively. In the Designer Device Selection wizard, you can now specify VCCA and VCCI voltages as 1.2 volt, 1.2–1.5 volt, or 1.5 volt for the v2 devices above. Where 1.2 V-1.5 V is selected, the SmartPower Operating Conditions dialog allows you to select a voltage at any point within the range prior to layout for VCCA and VCCI, and visualize the power consumption.
Project Manager
- An I/O Attribute Editor is now available from the Libero IDE Project Manager. Pin assignments, I/O technologies, and attributes, such as slew rate and drive strength, can now be set during the pre-netlist design phase and included as part of a SmartDesign. Existing PDC files can be opened and displayed within the editor. This does not replace the I/O Attribute Editor in Designer MultiView Navigator. The pre-netlist I/O Attributes are passed to Designer, and used by the MultiView Navigator I/O Attribute editor where attributes can be modified, if necessary. The updated file can then be passed back to the Project Manager for synchronization.
- The Tool Profiles management has been enhanced to improve usability. This new implementation allows you to better distinguish the tool profiles installed with Libero IDE v8.5 as they are shown with a padlock icon from your Tool Profiles. The profiles shown with a padlock icon can not be modified as they are locked to the specific Libero IDE installation. If you need to run a tool in batch mode or use a different tool version then you can define a new Tool Profile. Importing a Tool Profile INI file will overwrite your current Profiles with all Profiles defined in the INI file. Opening a project with a different Profile will change only the selection of your active Profile. If the project uses a Profile name that is not defined in your current Profiles, then this new Profile will not be restored in the current Profiles list when opening the project. In that case, you must define this new user Profile before opening the project.
- The DirectCore installation and update process has been improved. Prior to v8.5, installation of a new core or new core version was a manual operation using the Add Core to Vault dialog. In v8.5, there are options for: (1) an automatic mode, where new DirectCores are automatically downloaded at startup, or (2) a standard mode, where a tool tip informs you of new cores, with a hyperlink where you can choose to directly download the latest version of a core.
SmartDesign
- CoreConsole project conversion is now available. Projects previously created with CoreConsole, or CoreConsole projects in process, can be automatically converted to a SmartDesign project. When opening an existing CoreConsole project in the Project Manager, you are asked if you want to convert the project into a SmartDesign. When converted to SmartDesign, the original CoreConsole design is saved separately outside of Libero IDE.
- The I/O Attribute Editor view is available, where you can assign pins and set I/O attributes for the respective SmartDesign Project. SmartDesign will automatically generate a PDC file and pass it to Designer.
- A "Save As" feature is now available, enabling you to save your SmartDesign component with a new name.
- The "Connectivity Checker" has been renamed as "Design Rule Checker".
SmartPower
- Pre-defined Scenarios for each device family provide pre-set operating mode and time duration combination 'templates' that represent typical real-life operating conditions in various applications. Average power consumption for each template can quickly be viewed. Additional scenarios can be easily constructed, tested, and added to the project.
- Mode selection for power-driven layout has been added. The Layout Options dialog now allows you to drive power-driven layout based on a specific operating mode, such as Active, Sleep, etc. This feature drives layout to achieve the lowest possible power for the selected mode.
- Asynchronous detection is now available. By identifying Set/Reset signals of registers and memories, SmartPower assigns a very low toggling frequency for these asynchronous signals. This is especially important when Set/Reset signals have been assigned to a global resource. Initializing these signals with the higher default toggle rate would lead to overestimating their power consumption.
SmartTime
- Tracking jitter and clock-to-clock uncertainty constraint is added. Tracking jitter is the variation of clock edge position of the PLL outputs with reference to the PLL input clock edge. A clock-to-clock uncertainty constraint has been included that helps model the tracking jitter. SmartTime now automatically creates clock-to-clock uncertainty constraints to model the tracking jitter in clock control circuit (CCC). As a result, inter-clock domain slacks between the input clock of the CCC and the output clocks see a reduction of 400 ps, if the CCC is configured in the slow lock mode, and 800 ps, if configured in the fast lock mode. This is implemented for Fusion, IGLOO, IGLOO PLUS, ProASIC3, and ProASIC3E. Existing designs may realize a change in timing as a result of this feature.
- The Bottleneck Analysis view now includes a helpful interactive color graph that displays cells versus path cost. Clicking on a specific data point in the chart displays the associated timing details in the data grid.
- The Timing Analysis view now includes a color graph of passing and violating paths with respective slack values. Clicking on a specific data point in the chart displays the associated timing details in the data grid.
- The Expanded Path view now includes a summary of parallel paths, plus a "Path Profile" color chart that displays cell delays versus net delays. The summary allows user to quickly see the details of each parallel path.
Block Flow
Designer now attempts to preserve routing when you move a block. This feature is useful when implementing multiple blocks, or instantiating the same block multiple times, and you have to manually move the block for floorplanning. This feature is supported for Fusion, IGLOO, and ProASIC3 devices.
SIMBUF Logical Macro
A SIMBUF macro can be added to the design that provides a virtual logical buffer for observation in simulation. This feature allows you to probe internal nets and see their values during simulation, both pre-/post-synthesis and post-layout. Without this feature, the net names can change during synthesis or in Designer, and you would need to update the test bench with the updated net names. The SIMBUF macro includes a "D" pin that can be connected to the internal net and a PAD of an external port. The SIMBUF is not an I/O (but is a virtual I/O), and it will be optimized out by Designer. It is viewable only in the NetlistViewer and the back-annotated netlist. You must manually instantiate the SIMBUF macro. It causes zero delays in simulation. SIMBUF is supported by Synplify Pro/Synplify AE 9.6A, and is available for Fusion, IGLOO, ProASIC3, and Axcelerator families.
ProASIC3L Characterized Timing
The ProASIC3L timing models in SmartTime are now based on characterized silicon.
FlashPro v8.5
Read the FlashPro v8.5 release notes for latest features and details.
New Devices
IGLOO nano
| Device |
Feature Grade* |
Package |
Speed Grade |
Temperature Range |
| AGLN030V2 |
Z |
QN48,
QN68, CS81, µC81, VQ100 |
STD |
COM, IND |
| AGLN030V5 |
ProASIC3 nano
| Device |
Feature Grade* |
Package |
Speed Grade |
Temperature Range |
| A3PN030 |
Z |
QN48,
QN68, VQ100 |
STD, -1, -2 |
COM, IND |
* IGLOO nano and ProASIC3 nano 'Z' devices are available now for designs that do not require the use of Schmitt trigger, hot swap capability, or bus hold in the Flash*Freeze mode (IGLOO nano only). The programming file generated for a nano 'Z' design can be used to program both 'Z' (available now) and standard nano devices as they become available.
RTAX-DSP
| Device |
Package |
Speed Grade |
Temperature Range |
| RTAX2000D |
1152 CCGA/LGA† |
STD |
MIL |
| RTAX4000D |
1272 CCGA/LGA |
STD |
MIL |
† Note: The CG1152 package for RTAX2000D will be replaced with a CG1272 package in a future release.
New Packages and Options
IGLOO nano
| Device |
Package |
Speed Grade |
Temperature Range |
| AGLN010V2 |
µCS36 |
STD |
COM, IND |
| AGLN010V5 |
ProASIC3
| Device |
Package |
Speed Grade |
Temperature Range |
| M1A3P1000 |
PQ208, FG144 |
STD, -1 |
MIL |
Programming File Generation
Programming file generation is enabled for:
- M1AGL1000V2
- M1AGL1000V5
- M1A3P600L
- M1A3P1000L
- Synplicity Synplify/Synplify Pro AE 9.6A
- Mentor Graphics ModelSim AE 6.4a
- SynaptiCAD WaveFormer Lite 12.30a
- Actel FlashPro v8.5
- Enhanced feature has been to manage I/O Settings during programming. The Manage Used I/O Settings During Programming option has been removed from the Designer MultiView Navigator I/O Attributes Editor and moved into Designer FlashPoint and FlashPro. You can now manage unused I/Os as well as used I/Os.
- Automatic chain construction is now available. FlashPro will scan all attached programmers and automatically display a chain of all devices according to their respective programmer.
- FlashPro will now automatically import nonvolatile memory (NVM) .efc and FlashROM .ufc configuration files from a netlist.
- Read the FlashPro v8.5 release notes for more information including SAR fixes.
- Actel Silicon Explorer v5.2
The following software tools are all included in the Libero IDE v8.5 Windows DVD or are individually available for download from Actel.com. Release notes and other information are also available.
Libero IDE v8.5 is supported on Windows Vista Business, Windows XP Pro, and Red Hat Linux 4.0 and 5.0.
For more information, view the complete System Requirements.
Libero IDE v8.5 requires a current Libero IDE v8.0 license. Register for a free Libero IDE Evaluation or Gold license, or contact your local Actel Sales office to purchase a Libero IDE Platinum license.
Unless otherwise noted, these issues apply to all devices.
Project Manager
13024 - Analog channels must be assigned to specific package pins on the package.
The I/O Constraint Editor in the Project Manager allows users to assign Analog channels to invalid analog package pins.
Users should not use the I/O Constraint Editor in Project Manager or SmartDesign to assign package pins to the analog channels. Use the Analog System Builder to do the package pin assignments.
12501/12872 - "Command set_ioattr Parsing failed" message appears when updating an Analog System Builder block (Fusion)
After creating and configuring an Analog System Builder (ASB) block and instantiating it into SmartDesign, and reconfiguring the ASB by adding more channels, and reconciling the block in SmartDesign by selecting Update with the latest version option, the following messages will appear for each analog channel:
Command set_ioattr Parsing failed. Aborting script. Line: set_ioattr -io v1
SLEW High Low
Command set_ioattr is a no-op assuming failed - but continuing script
Workaround: The messages can be ignored.
12208 - After configuring the CoreEDAC with the default option "Create internal RAM Block with full EDAC support," you must refresh the Design Hierarchy. Otherwise, the RAM block is not placed in the hierarchy.
Simulation and synthesis will both fail.
Required user action: Refresh the design hierarchy by using <CTRL>+R in the Design Hierarchy window, or by using View > Refresh Design Hierarchy, after the CoreEDAC (including an internal RAM block) is generated.
14287 - Refer to 12208 above.
12208 addresses CoreEDAC. However, this refresh issue is more general and affects any configured core, including licensed obfuscated cores.
When these cores are configured via the Libero IDE catalog, a "?" mark is associated to the core name itself in the Design Hierarchy tab.
Required user action: To remove the "?" and exhibit the core in the hierarchy, refresh the design hierarchy by using <CTRL>+R in the Design Hierarchy window, or by using View > Refresh Design Hierarchy, after the core is generated.
12148 – Comments in an existing PDC file are not saved when opened with the I/O Attribute Editor
If you want to preserve comments in a PDC file, open the PDC with the text editor and save it as a separate PDC file. The PDC file can be viewed and edited in the I/O Attribute Editor. However, comments are not viewable in the grid. Saving any edits will overwrite the file and the comments will be lost.
Libero IDE Catalog
12209 – CoreEDAC must be used with Libero IDE v8.5
When available, the CoreEDAC must be used with Libero IDE v8.5. It can not be used with pre-v8.5 versions.
SmartDesign
14952 - GND/VCC attribute symbol is missing in grid when upgrading design to v8.5 with Linux
When converting pre-Libero IDE v8.5 SmartDesigns to v8.5, GND and VCC (tie-high, tie-low) symbols are missing in the Attribute column.
Designer
12915 – FlashPoint displays incorrect NVM blocks for designs in post-layout state that are created with a pre-v8.5 release.
This problem occurs if a new netlist is imported after the programming files were generated, as in the following example:
- Using pre-v8.5 version of Designer, create a new Fusion design. Import a netlist that has a NVM block (NVM1).
- Run compile, layout, and generate programming files and save the design.
- Import a second netlist that has a different NVM block (NVM2).
- Run all steps including Layout but do not generate the programming files.
- Save the design.
- Open the adb using Designer v8.5.
- Open FlashPoint, and it only displays the NVM1 block that was imported from the original netlist.
Workaround: Import netlists, compile, and layout using Designer v8.5 only.
12910 – With v8.5, the FlashROM (FROM) content is missing from the generated programming file when using a pre-v8.1 netlist.
This problem occurs only when creating a new design with Libero IDE/Designer v8.5 and using a netlist that was created by a pre-v8.1 version of Libero IDE/Smartgen. When re-opening FlashPoint after programming file generation, you will see an error message next to the FROM feature stating that the FROM data cannot be loaded. Also, if you open the .stp file, the FROM content will be missing.
Workaround: Save design and re-import .ufc file; then, regenerate the programming files.
12814 – Exporting only a DAT file via TCL script will fail
Designer will fail to export a DAT file, if you use a TCL script that only has 'dc' as an export file type. The following error message will be displayed:
Problem: "Syntax error when executing TCL scripts that generate only DirectC file (*.dat)"
Error: export: unknown file type dc
Error: The command [export] failed with error code 0x80004005
Error: Failure when executing Tcl script. [ Line 10 ]
Workaround:
- Export new TCL script
- Select an additional output format along with "DirectC File (*.dat)"
Example: Select "Programming Data File (*.pdb)" and "DirectC File (*.dat)"
- Execute TCL script
12552 – To preserve the Synplify inferred soft Triple Module Redundancy (TMR) blocks for RT3PE600L or RT3PE3000L devices, users should NOT:
- Run advanced layout using sequential optimization
- Use the I/O-register combining option in compile, MVN I/O Attribute Editor, or in Tcl
Either of these features may optimize out one or more register macros from the soft TMR blocks cells optimized out in Layout.
SmartTime
12376 – Handling of combinational paths through the RTAX2000D and RTAX4000D math block.
RTAX-DSP designs containing a non-pipelined MATH18X18 macro (output P configured as not-registered) would have its combinational data-paths unrecognized by SmartTime. SmartTime critical-path analysis omits analyzing such data-paths and this may sometimes cause it to predict a more optimistic performance. Back-annotated simulation should be used to validate the timing of designs with non-pipelined MATH18X18 macros. Users relying on SmartTime analysis are advised to always design any MATH18X18 macro with its output P configured as registered.
Programming File Generation
14989 – STAPL file version dependency for UMC ProASIC3 FPGAs
In April 2008, Actel made a 1-bit modification to the UMC ProASIC3 device IDCODE which is programmed into each device produced by Actel. Correspondingly, Actel accounted for this device IDCODE update in the Libero IDE and Designer software such that ProASIC3 STAPL files generated by Designer would contain IDCODEs that would match with the IDCODE in the ProASIC3 silicon. Combining the new ProASIC3 silicon with an old STAPL file results in a programming failure since the IDCODE in the new device does not match the IDCODE expected by the old STAPL file. The resulting error message is "Exit 6 – Failed to verify IDCODE".
REQUIRED CUSTOMER ACTION:
UMC ProASIC3 silicon with date code later than "0816" must be programmed with a STAPL file generated by Libero IDE/Designer v8.2 (capture 8.2.0.17) or later.
UMC ProASIC3 silicon with a date code of "0816" or earlier will have an old IDCODE, but a STAPL file generated from Libero IDE/Designer v8.2 (capture 8.2.0.17) or later will be backwards compatible with the older devices.
Programming/FlashPro
12564 – Export Chain STAPL/SVF fails if the source file is STAPL.
Error message when exporting Chain SVF:
Cannot export SVF files. SVF is not supported for selected device.
Error message when exporting Chain STAPL:
Failed to export chain STAPL file '<filename>'
Workaround:
- Use PDB file as source file instead of STAPL
- Use FlashPro version prior to v8.5
11138/12637 – Pre v8.5 adb loses I/O settings in Compile.
In v8.5, the I/O state during programming has been removed from the I/O Attribute Editor and PDC. If you run a pre-v8.5 adb using v8.5, all previous I/O settings will be lost and I/Os will be defaulted to tri-state.
Workaround: To save previous I/O settings, generate the programming file and save the adb.
BSDL File Generation
12640 - Incorrect BSDL file data is generated after the initial run, affecting all Fusion, IGLOO, and ProASIC3 families. (Linux)
Workaround: Use a Windows PC for BSDL file generation, or only use the data from the first run.
IEEE 1532 Generation
12639 – IEEE 1532 generated files have syntax errors. (Linux)
Workaround: Use a Windows PC for IEEE 1532 file generation.
Customers should refer to their respective Techinal Support Hotline case number. If a Software Action Request (SAR) was created for the case and it has been fixed in this Libero IDE release, the number will be on the list below.
- 8868
- 8880
- 9055
- 9180
- 9347
- 9367
- 9400
- 9503
- 9541
- 9899
- 10037
- 10515
- 10523
- 10589
- 10862
- 12544
- 34281
- 52646
- 70105
- 70535
- 71403
- 72136
- 73055
- 73990
- 74226
- 74424
- 74843
- 74887
- 75209
- 75210
- 75471
- 75493
- 76139
- 76717
- 76942
- 77063
- 77252
- 77328
- 77536
- 77568
- 77631
- 77855
- 78078
- 78096
- 78178
Choose one of the following, depending on your system's operating system - Capture 8.5.0.34:
