Libero IDE v8.4 Service Pack 1 (SP1) Release Notes
(updated on Oct 27, 2008)
Thank you for your interest in Actel's Libero Integrated Design Environment (IDE) v8.4 Service Pack 1.
What's New in this Service Pack
IGLOO nano and ProASIC3 nano Introductions
Libero IDE v8.4 SP1 introduces full design flow support for the initial offering of Actel's IGLOO nano and ProASIC3 nano devices. Evolved from IGLOO and ProASIC3 families, the nano devices offer tremendous value and flexibility for high volume markets. Competitively priced in the market, nano devices are perfect ASIC or ASSP replacements while retaining the historical FPGA advantages of flexibility and quick time-to-market, low cost, low power, and compact designs. Devices and packages offered in SP1 are noted below:
| IGLOO nano |
Feature Grade* |
Package |
Speed Grade |
Temperature Range |
| AGLN060V2 |
Z |
100 VQFP |
STD |
COM, IND |
| AGLN060V5 |
| AGLN125V2 |
Z |
100 VQFP |
STD |
COM, IND |
| AGLN125V5 |
| AGLN250V2 |
Z |
100 VQFP |
STD |
COM, IND |
| AGLN250V5 |
| ProASIC3 nano |
Feature Grade* |
Package |
Speed Grade |
Temperature Range |
| A3PN060 |
Z |
100 VQFP |
STD, -1, -2 |
COM, IND |
| A3PN125 |
| A3PN250 |
* IGLOO nano and ProASIC3 nano 'Z' devices are available now for designs that do not require the use of Schmitt trigger, hot swap capability, or bus hold in the Flash*Freeze mode (IGLOO nano only). The programming file generated for a nano 'Z' design can be used to program both 'Z' (available now) and standard nano devices as they become available.
RT ProASIC3L
Libero IDE v8.4 SP1 introduces support for Actel's new radiation-tolerant low-power ProASIC3L devices. See device details in the ProASIC3L web page. Synplify 9.4.1A, included with Libero v8.4, includes TMR (Triple Module Redundancy) support for RT ProASIC3EL devices. See details in the Synplify 9.4.1A section of these release notes.
RT ProASIC3 Timing Derating
This release includes a capability to derate RT ProASIC3 timing by 10% to account for 15 krad total ionizing dose (TID) exposure.
New Device Support
The following devices and packages are supported in this release:
| Fusion |
Package |
Speed Grade |
Temperature Range |
| P1AFS600 |
256 FBGA |
-2 only;
-1 has been removed. |
COM, IND |
| 484 FBGA |
| P1AFS1500 |
256 FBGA |
-2 only;
-1 has been removed. |
COM, IND |
| 484 FBGA |
| IGLOO |
Package |
Speed Grade |
Temperature Range |
| AGL400V2 |
144 FBGA |
STD |
COM, IND |
| 256 FBGA |
| AGL400V5 |
144 FBGA |
STD |
COM, IND |
| 256 FBGA |
| AGL1000V2 |
CS281 |
STD |
COM, IND |
| AGL1000V5 |
| M1AGLE3000V2 |
484 FBGA |
STD |
COM, IND |
| 896 FBGA |
| M1AGLE3000V5 |
484 FBGA |
STD |
COM, IND |
| 896 FBGA |
| IGLOO PLUS |
Package |
Speed Grade |
Temperature Range |
| AGLP030V2 |
128 VQ |
STD |
COM, IND |
| AGLP030V5 |
| AGLP060V2 |
176 VQ |
STD |
COM, IND |
| AGLP060V5 |
| ProASIC3 |
Package |
Speed Grade |
Temperature Range |
| A3P125 |
132 QFN |
STD, -1 |
T(Grade 1),
T(Grade 2) |
| A3P1000 |
208 PQFP |
STD, -1 |
MIL |
| ProASIC3L |
Package |
Speed Grade |
Temperature Range |
| A3PE600L |
484 FBGA |
STD, -1 |
MIL |
| A3P1000L |
144 FBGA |
STD, -1 |
COM, IND |
| 208 PQFP |
| RT3PE600L |
484 CCGA/LGA |
STD, -1 |
MIL |
| RT3PE3000L |
484 CCGA/LGA |
STD, -1 |
MIL |
| 896 CCGA/LGA |
| M1A3P1000L |
144 FBGA |
STD, -1 |
COM, IND |
| 208 PQFP |
| 256 FBGA |
| 484 FBGA |
| RTAX-S |
Package |
Speed Grade |
Temperature Range |
| RTAX250S |
624 CCGA/LGA |
STD, -1 |
MIL |
Fusion
For all devices, the temperature derating has been changed for the flash memory nonvolatile memory (NVM) minimum pulse width and the min period.
Prior to 8.4 SP1: There was no derating over temperature.
| Temperature |
Speed Grade |
| -2 Device |
-1 Device |
STD Device |
| 70°C |
100 MHz |
80 MHz |
80 MHz |
| 85°C |
100 MHz |
80 MHz |
80 MHz |
| 100°C |
100 MHz |
80 MHz |
80 MHz |
New to 8.4 SP1: Derating factor of 1.25 applies at 100°C as shown below.
| Temperature |
Speed Grade |
| -2 Device |
-1 Device |
STD Device |
| 70°C |
100 MHz |
80 MHz |
80 MHz |
| 85°C |
100 MHz |
80 MHz |
80 MHz |
| 100°C |
80 MHz |
64 MHz |
64 MHz |
Programming File Generation
Programming file generation is enabled for the following devices:
FlashPro v8.4 SP1
FlashPro v8.4 SP1 is included in Libero IDE v8.4 SP1. Read the FlashPro v8.4 SP1 release notes for latest features and details.
Important Information for Fusion, IGLOO, IGLOO PLUS, ProASIC3, and ProASIC3L Users
Any two-port RAM configuration (RAM512X18) for Fusion, IGLOO, IGLOO PLUS, ProASIC3, and ProASIC3L with both read and write widths of 9 bits is not supported by Libero IDE/Designer versions prior to 8.4 SP1. SmartGen does not generate such RAM configurations. However, they could have come from the synthesis tool inference or a manual generation by the user. These configurations were not detected by Designer, leading to time-zero failures in the silicon.
Libero IDE/Designer 8.4 SP1 supports this RAM configuration. If you open an existing design using v8.4 SP1 with such a RAM configuration, Designer will display the following message instructing the user about fixing the issue:
Error: The design has an invalid RAM configuration. Invalidating Compile. Compile must be re-run.
You can preserve your existing Layout by running the placer with Incremental Mode "FIX" and the router with Incremental Mode "ON".
Synplify 9.4.1A TMR Support for RT ProASIC3EL Devices
This feature can be turned on in Synplify SCOPE attribute editor.
The attribute can be also be set in the source code (Verilog/VHDL) or in .sdc (Synplify design constraint) file.
syn_radhardlevel attribute has following values:
none - standard design techniques are used
tmr - Tripe module redundancy or triple-voting is used to implement registers. Each register is implemented by three flip-flops or latches to determine the state of the register.
Setting the attribute in .sdc and source files:
.sdc File Syntax and Example:
define_attribute { object } syn_radhardlevel { none | tmr }
where object is a module/architecture/register. For example:
define_attribute {dataout[3:0]} syn_radhardlevel {tmr}
Verilog Syntax and Example:
object /* synthesis syn_radhardlevel ="none | tmr " */ ;
where object is an output signal. For example:
module top (clk, dataout, a, b);
input clk;
input a;
input b;
output dataout [3:0];
reg [3:0] dataout /* synthesis syn_radhardlevel="tmr" */;
// Other code
VHDL Syntax and Example:
attribute syn_radhardlevel of object : objectType is " none | tmr " ;
where object is a module/architecture/register. objectType is architecture or signal.
library synplify;
architecture top of top is
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of top: architecture is "tmr";
Known Issues
9527 – Definitions specified in a package file are not passed to SmartDesign.
If an entity/architecture definition has some constants or functions defined in a VHDL package then this entity cannot be instantiated into SmartDesign.
An error pops up saying that the VHDL file has syntax errors. The user can disregard this error because even if the file does not have any syntax errors, the definitions in the package are not supplied to SmartDesign, and the component cannot be instantiated.
10728 – Synplify 9.4.1A does not include part numbers RT3PE600L and RT3PE3000L.
Workaround: Click OK in the Synplify dialogs, and Synplify will change the device type to A3P250L. After Synthesis, Designer will retain the original device type RT3PE600L or RT3PE3000L.
Download Libero IDE v8.4 SP1
The version of software that you requested is no longer the most current version available. Please download the most recent software update.
If you need this specific version of software, please contact Actel Tech Support:
Email: tech@actel.com
Phone: 1.800.262.1060
