Libero IDE v8.4 Release Notes
(updated on Nov 5, 2008)
Thank you for your interest in Actel's Libero Integrated Design Environment
(IDE) v8.4.
Libero IDE Gold includes expanded device coverage
As of this release, all 1.5 million gate devices are now included in the Free Libero IDE Gold license edition.
SmartDesign
SmartDesign has been re-designed to replace CoreConsole and enable fast creation of simple to complex System on Chip (SoC) designs including processor/bus-based and Fusion mixed-signal designs. Complete FPGA systems and subsystems can be designed in minutes by selecting from Actel's core libraries, making quick and error-free connections, and automatically creating a synthesis ready HDL file.
Key Features:
- Visual block-based design creation tool
- Replaces CoreConsole for processor, bus-based, and DirectCore subsystem creation
- Quickly select, configure, and connect proven functional blocks from Libero IDE Catalog: DirectCores, Smartgen Cores, and Actel cells
- Import and connect user-generated IP, Designer "Blocks", and custom/glue-logic HDL modules including ViewDraw schematic modules
- SmartGuide guidance suggests compatible interfaces and makes note of required peripherals
- All construction is performed on a single "Canvas" view
- All pins/ports are exposed and ready for connection on the Canvas view
- Automatic or simple point-and-click manual connections
- Design-rule check disallows improper connections or unconnected ports
- Dynamic audit system informs of out-of-date configurations
- Automatic abstraction to synthesis-ready HDL
- Efficient construction of complex processor, bus based, Fusion mixed-signal, and simple designs
- Complete FPGA SoC, FPGA subsystem, or embedded SmartDesign-in-SmartDesign
SmartPower Analysis
SmartPower has been enhanced to include several new features providing:
- Better visual display of power breakdowns through use of pie charts
- Simplified tabs for Domains and Enable Rates
- An improved VCD import flow
- An interactive graphical interface for Peak Power analysis where you can view power data by clock cycle and time increments
- A new docking window in the main view where you can create and display Modes and Scenarios. The window displays all default modes, plus any new modes or scenarios that have been created.
- Dialogs to create, test, and save multiple operating "Scenarios" within the project
- Worst and best case operating conditions for Fusion are now supported
Power and Power Reduction
- Power-Driven Place-and-Route (PDPR) is now available for Axcelerator AX and RTAX-S devices. PDPR is an option from the Layout menu and can reduce the total dynamic power of a design up to 10%, with minimal impact on timing.
- Additional power reduction may occur when using a new power-sensitive multi-seed layout option available from the Layout Options menu. The "power aware" multi-seed layout option is available for Fusion, ProASIC3, ProASIC3L, IGLOO, IGLOO PLUS, and Axcelerator devices.
- SmartGen configuration of Fusion, IGLOO, IGLOO PLUS, ProASIC3, and ProASIC3L RAM cores within the Libero IDE catalog now have a 'low power' option. The low power option can reduce power consumption up to 75% in the largest configuration (8k x 4). A performance reduction will occur. Timing performance should be analyzed after layout.
- Power consumption data for Fusion devices is now based on characterized silicon data.
Project Manager
- The default opening of the Project Manager interface now has the Libero IDE catalog on the right side of the Design Flow/SmartDesign window. The Hierarchy/Files window remains on the left side. This provides a more efficient layout of all windows. All windows are un-dockable and can be moved or hidden to suit your viewing preference.
- DirectCore IP is managed within a new Libero IDE "Repository Manager". Libero IDE will display a message on the lower Catalog frame when a new DirectCore or core version is available from the Actel Repository. Use the "Add Core – From Web Depository" selections in the Catalog and download new core or new core versions. You can also direct the Repository Manager to manage or monitor other repositories. CoreConsole is no longer needed for DirectCore version import or management.
- The Find toolbar is enhanced to encompass and eliminate all other various Find tools. A single Find tool allows you to search for Ports/Nets/Instances in SmartDesign, text in the Text Editor, search in Libero IDE files, or search the entire project. The Find toolbar is "on" by default and can be undocked or hidden.
- EDIF Flow Support. You can now import an EDIF netlist into the project that has been created by 'full up' ViewDraw versions.
Expanded Core Voltage Range for IGLOO, IGLOO PLUS, and ProASIC3L devices
A "wide-range" operating voltage (VCCA only) is available for A3PL, AGL-V2, AGLE-V2, and AGLP-V2 devices. With these devices the VCCA core voltage can be selected for operation at any point in the range of 1.14 V to 1.575 V. The VCCI I/O voltage must be consistent with available I/Os (1.2 V, 1.5 V, etc) and equal to or higher than the VCCA voltage. Using v8.4 Device Selection wizard in Designer, designs for these devices can be set to operate at any point between 1.14 and 1.575 volts, providing system designers flexibility for power supply options such as dual voltage, dynamic voltage/frequency scaling, and unregulated battery applications. A potential application for this feature is to maintain core functionality for long periods of time (via a battery), so system functionality is ensured when the entire device is made active. Dual/Dynamic voltage applications could have the device run at a higher voltage within the range for active functions and then at the lower voltage for Flash*Freeze for even lower power consumption, or the standard active mode may operate at the lower voltage and a 'burst-mode' higher speed function at the higher end of the voltage range.
SmartTime
- Combinational Loops Report. Combinational loops may occur in designs either intentionally or unintentionally. A combinational loop must be broken between two pins for timing analysis to present accurate delay timing. A new combinational loops report displays all loops found during SmartTime initialization, listing the pins associated with a loop or multiple loops sharing common pins, and noting the location of where the loop has been broken for analysis. Users also have control of where loops are broken through a dialog, and for Tcl users, a new command 'set_disable_timing' allows users to set where a combinational loop is broken.
- Breakdown by Clock Domain has been added to the Constraints Coverage report. Constraints that show as 'untested' now have explanations, such as 'missing clocks'. A tcl command report –type "constraints_coverage" is also available for this report.
- Enhanced Min Delay 'best case' values can now be exported in the SDF file. (Fusion, IGLOO, IGLOO PLUS, ProASIC3, and ProASIC3L devices).
- Clk-to-out delays for the IGLOO and IGLOO PLUS FROM and FROMH have been updated. The updated data specification is available in their respective datasheet.
IGLOO Devices/Packages
New Devices
| Device |
Package |
Speed Grade |
Temperature Range |
| M1AGL1000V2 |
CS281, FG144, FG256, FG484 |
STD |
COM, IND |
| M1AGL1000V5 |
New Packages
| Device |
Package |
Speed Grade |
Temperature Range |
| AGL060V2 |
QN132 |
STD |
COM, IND |
| AGL060V5 |
ProASIC3E New Devices
| Device |
Package |
Speed Grade |
Temperature Range |
| M1A3PE3000* |
PQ208, FG324, FG484, FG896 |
STD |
COM, IND |
* Programming File generation is enabled in this release.
Military Temperature Range for ProASIC3L A3PE3000L
MIL temperature operation is now available for the ProASIC3L A3PE3000L device in FG484 and FG896 packages. Standard and -1 speed grades are offered.
Repair of Minimum Delay Violations
The Advanced Layout Option for repair of minimum delay violations for Axcelerator devices (AX only) has been enhanced to take advantage of programmable delays on I/O Input buffers. The feature inserts delay in paths where the minimum delay in not being met, while simultaneously checking maximum delays to ensure no violations are being introduced. This feature is not supported for RTAX-S devices.
Performance Improvement for Fusion, IGLOO, IGLOO PLUS, and ProASIC3L
A new 'Sequential Optimization' option is available on the Advanced Layout dialog in Designer. Using this feature, some designs can realize performance improvement up to 30%. This option turns on the optimization of sequential cells in the High Effort Layout mode. This typically enables register retiming without disturbing timing latency. The names of registers may change unless they are assigned a physical constraint (locked at a location, assigned to a region, or part of a block component), referred in a timing constraint, or have a preserve property. Other restrictions may also apply.
ViewDraw
A 'Save and Check All' option has been added to the ViewDraw toolbar. This option updates all wir files and ensures that they are synchronized with the schematic files.
FlashPro v8.4
Read the FlashPro v8.4 release notes for latest features and details.
If you are designing with the AFS600 or AFS1500 and are experiencing a failure when using Silicon Sculptor to program the FPGA with a STAPL file generated using Libero IDE v8.4, use a STAPL file generated with
Libero IDE v8.3 SP1 or an earlier version to program the FPGA. If you still need to use STAPL file from Libero IDE v8.4 to program your FPGA using Silicon Sculptor, please
contact Actel Tech Support for more information.
During the Libero IDE installation, the ModelSim pre-compiled libraries may not be extracted. If the libraries are not extracted, simulation will fail.
Workaround:
- You will need a compression utility software that extracts a GZIP (GZ) file format.
- Navigate to the installation of the ModelSim pre-compiled libraries, typically C:\Libero84\Libero_v8.4\Designer\lib\modelsim\precompiled\vhdl or C:\Libero84\Libero_v8.4\Designer\lib\modelsim\precompiled\vlog
- Open the desired folder
- Manually extract the library for each family, as needed, to the current folder.
-
For example:
Double click on "fusion.tar.gz" to extract the Fusion pre-compiled libraries. Make sure that the extracted files reside in the folder per the path specified above, not a sub-folder.
Configurator.exe must be run before using ViewDraw in Libero IDE v8.4
A new version of Viewdraw is packaged in Libero IDE v8.4. Since Viewdraw versions can be co-installed on the same machine, users must manually run the configurator.exe located in the <Libero IDE v8.4 installation folder>/Viewdraw/bin folder. This operation ensures that there will not be any conflicts between the different Viewdraw installed versions. Note that when the configurator.exe is run, there is a popup message stating that a library cannot be loaded. This message can be ignored.
Back up your Libero IDE project before converting it into Libero IDE v8.4
When working with ViewDraw, it is recommended users backup pre- v8.4 project before converting it into v8.4. After conversion to v8.4, pre-v8.4 schematic files can not be opened by pre-Libero IDE v8.4 versions.
An Device Families XML file is available and must be installed when using CoreConsole standalone, or when using CoreConsole standalone and then importing the CoreConsole generated file into Libero IDE. This update is required for CoreConsole v1.4 to recognize and deal with Cortex-M1-specific devices that became available since the CoreConsole v1.4 release and which are or will be supported by CDBs in existing or future Cortex-M1 CCZ releases. The devices for a specific CDB must be in Device Families XML file for use of that Cortex-M1 variant to be used and for the CoreConsole design to generate and import into Libero properly. The Device Families XML file is a configuration file used by CoreConsole v1.4 for mapping between Libero IDE device family names, IP core device FAMILY configuration parameter ID values, and Libero/CoreConsole/IP core die names. The file is integral to how CoreConsole performs design rule checks and how it generates the appropriate CXF file family/die related metadata.
The specific devices added in this update are:
ProASIC3
- M1A3P250L
- M1A3P600L
- M1A3P1000L
- M1A3PE3000L
Fusion
To install this Device Families XML file, follow these steps:
- Make a backup copy of your existing <CoreConsole installation folder>/DeviceFamilies.xml file
- Unzip the provided ZIP file and copy the enclosed DeviceFamilies.xml file into the root folder of your CoreConsole installation to overwrite the original v1.4 version
Using either CoreConsole standalone or as part of Libero IDE, failure to install the update and attempting to use a Cortex-M1 CDB targeting one of the above devices will result in a pre-generate validation error:
- Request Failed
- CoreConsole could not fulfil your request.
- Invalid die selection for CortexM1_00.
M1A3P600L does not belong to device family ProASIC3. Verify that component instances with a device family choice are set to a value consistent with component instances that have a die choice.
To use any of the above devices with the CortexM1 core, you must download and install v2.5, which will be available in mid-August.
If CoreRSDEC, CoreRSENC, or CoreABC are to be used in a Libero IDE v8.4 project, with or without SmartDesign, CoreConsole v1.4 must be installed and a profile set in the Libero IDE Project Manager. When using SmartDesign, CoreConsole is required for configuration of these cores, afterwhich they will be instantiated onto the SmartDesign canvas. If you do not have CoreConsole v1.4 installed configuration dialogs will not open. CoreConsole 1.4 is available for download. Licenses for CoreConsole and these DirectCores are available within the Libero IDE license bundles.
- Synplicity Synplify/Synplify Pro AE 9.4A
- Includes new device support and bug fixes
- Mentor Graphics ModelSim AE 6.3g
- Includes new device support and bug fixes
- SynaptiCAD WaveFormer Lite 12.30a
- Includes new device support and bug fixes
- Actel FlashPro v8.4
- Includes new device support and bug fixes
- Actel Silicon Explorer v5.2
The following software tools are all included in the Libero IDE v8.4 Windows DVD or are individually available for download from Actel.com. Release notes and other information is also available.
Libero IDE v8.4 is supported on Windows Vista Business, Windows XP Pro, and Red Hat Linux 4.0 and 5.0.
See Known Issues below regarding Windows Vista.
For more information, view the complete System Requirements.
Libero IDE v8.4 requires a current Libero IDE v8.0 license. Register for a free Libero IDE Evaluation or Gold license, or contact your local Actel Sales office to purchase a Libero IDE Platinum license.
Unless otherwise noted, these issues apply to all devices.
Project Manager
8852 - SDC file bundled with a DSP block is not automatically supplied to Synplify
Libero IDE v8.3 does not contain a "synthesis constraint files" list. The SDC was always passed, even though the user did not ask to pass it.
In v8.4, Libero IDE introduces a new list and dialog where you can organize the synthesis constraint files. A bug was also fixed so that default CXF settings are not restored upon opening.
When you open a v8.3 project with v8.4, the synthesis constraint list is empty (as it did not exist in v8.3), and it is not restored by the CXF. As a result, the SDC is not part of the synthesis constraint files; therefore, the list is not passed.
Workaround: Open the "Organize Constraint Files" dialog, and select to have the SDC file passed.
ViewDraw/Project Manager
8775 – Generating an EDIF file from the Tools/ViewDraw Tools pulldown causes Libero IDE to crash
For a pure structural netlist created with ViewDraw, you cannot directly generate the EDIF netlist from the menu: Tools > ViewDraw Tools > Generate EDIF. Doing so will cause the tool to crash.
Required action:
Within ViewDraw, click on 'Save & Check' to generate the HDL netlist and then run synthesis to get the EDIF file. This is also required for a pure structural netlist.
Design Explorer/Hierarchy
6064 - VHDL packages not be properly placed in the Design Hierarchy will cause simulation errors.
Occasionally, a VHDL package may not be properly imported into the Design Hierarchy. This will cause a simulation error to be generated.
Required action:
Refresh the design hierarchy display either with the <CTRL>-R shortcut, or close and reopen the project.
Identify/Project Manager
8768 – Identify AE 3.0A: Do not try to debug a design in Flash*Freeze mode
The Identify Debugger cannot get sampled values when the IGLOO/e design is operated in a Flash*Freeze mode. In Flash*Freeze mode, all the I/Os including the JTAG ports are assigned to a fixed value in this prevents the Debugger from communicating with the device. As a consequence, the Debugger never stops from performing data acquisition.
Required action:
Make sure that the design is operated in the active mode only while debugging with Identify.
8767 – Identify AE 3.0A crashes when incorrect cable type is selected
The Identify debugger will crash when you select the wrong cable type for the design project, e.g. IGLOO and FlashPro. You must select the appropriate cable type for the project device, in this case FlashPro3.
8766 – Identify: Sampler buffer type is set by default to 'Behavioral'
In Identify Instrumentor AE v3.0A, by default the Sampler buffer type is set to 'Behavioral'. This is not supported.
Required action:
Go to menu Actions => Configure IICE, and change the Sampler buffer type to 'deviceram'.
6023 – Cannot open the Identify BSP file if there is a space character in the path of the Libero project location.
Required action:
Make sure that there are no spaces in the path to the Libero project location.
Project Manager/Block Publishing
The Block publishing button "Publish Packager" is not available on Libero IDE Project Manager Design Flow window. You must use the "Generate Block" button in Designer in order to publish a Designer Block to the local disk. The "User Defined" category has also been removed from the Project Manager Catalog. To import the published Designer Block into a Libero IDE project, you must browse to and import the CXF file from the location where the Designer Block is saved.
SmartDesign
71632 – SmartDesign Generates Incorrect Bus Interface Connections when Users Connect an APB Bus Master to an APB3 Bus Master
Designer Layout
8785 – Flip Flop needs to be preserved through pdc if Fusion PLL designs runs through Sequential Optimization during P&R (Fusion)
Designer Linux
5448 – Large Number of Designer Sessions on Linux OS causes Designer to fail
SmartTime
2793 – Bus description in SDC should only use the convention used in the netlist
OEM Tools, Windows Vista
Mentor Graphics Precision 2008a does not run on Vista OS.
Synplicity Identify AE is not officially supported on Windows Vista and may not open on Vista OS machines.
Programming File Generation
8817 - Fusion STAPL files do not work with JAM and STAPL player (8.4)
Fusion STAPL files generated from Designer v8.4 or FlashPro v8.4 have syntax errors with JAM and STAPL players.
Workaround: Set DEF varilable ENABLE_CALIB_BACKUP to 0, then generate Fusion STAPL files.
DirectCore Vault
9021 – Make sure to have the write permissions on the files in the vault
If you do not have the write permissions to the DirectCore vault, you cannot generate a DirectCore, and a crash can occur.
Required action:
If different users must have an access to the DirectCore vault, you must perform a 'chmod 0777' on the entire tree, i.e. chmod -R 0777 *
DirectCore Configuration
6174 – CoreABC does not update the acmtable.v[hd] file w/ ACM
In previous CoreConsole implementations, if the user had configured a CoreAI and CoreABC in a design, the CoreABC generator would read the CoreAI configurations and export it into the acmtable.v[hd] file. This file contained the ACM configuration that the user specified for CoreAI. This update does not occur in Libero IDE v8.4. This only impacts users who use CoreABC with the "APBWRT ACM" instruction in CoreABC configurator.
CoreEDAC Use
12209 - CoreEDAC configuration will abort if opened in Libero IDE v8.4
Required action:
You must use CoreEDAC with Libero IDE v8.5.
