ProASIC3L
Libero IDE v8.2 introduces support for Actel's new low-power ProASIC3L devices that feature 40 percent lower dynamic power and 90 percent lower static power than its previous-generation ProASIC3 FPGAs. The new flash-based family combines dramatically reduced power consumption with up to 350 MHz operation.
The following devices and packages are available:
| Device |
Package |
Speed Grade |
Temperature Range |
| A3P250L |
VQ100, PQ208, FG144, FG256 |
STD, -1 |
COM, IND |
| A3P600L |
PQ208, FG144, FG256, FG484 |
STD, -1 |
COM, IND |
| A3P1000L |
PQ208, FG144, FG256, FG484 |
STD, -1 |
COM, IND |
| A3PE3000L |
PQ208, FG324, FG484, FG896 |
STD, -1 |
COM, IND |
Power-Driven Layout
Power-Driven Layout is available for the ProASIC3L devices. This Layout Options feature typically reduces the dynamic power consumption of a design by 10%.
ProASIC3L Programming Support
Programming File Generation is enabled for the A3P600L devices. Programming is available using FlashPro v6.2.
IGLOO
New Devices
| Device |
Package |
Speed Grade |
Temperature Range |
AGL250V2
AGL250V5 |
CS196 |
STD, -1 |
COM, IND |
AGLE3000V2
AGLE3000V5 |
FG484 |
STD, -1 |
COM, IND |
Characterized Timing Data
SmartTime timing data for the IGLOO family is now based on actual silicon characterization. Characterized timing data may have a minor performance affect on current designs.
Enhanced Min-delay
SmartTime now provides support for conservative minimum delay/hold-time analysis based on IGLOO characterized silicon timing data. This new feature eliminates the need to over guard-band a design for minimum delay, providing a more comprehensive, precise way to perform chip-to-chip evaluation of external setup/hold and clock-to-out timing.
ProASIC3
New Package Support
| Device |
Package |
Speed Grade |
Temperature Range |
| A3PE3000 |
FG484, FG896 |
STD, -1 |
COM, IND |
Programming Support
Programming File Generation is enabled for the M1A3P250 devices. Programming is available using FlashPro v6.2.
Characterized Power Data
SmartPower power data for the ProASIC3 family is now based on actual silicon characterization. Characterized power data may have a minor affect on current designs.
Fusion
Programming Support
Programming File Generation is enabled for the AFS1500 and M1AFS1500 devices. Programming is available using FlashPro v6.2.
Characterized Timing Data
SmartTime timing data for Fusion devices is now based on actual silicon characterization. Characterized timing data may have a minor performance affect on current designs.
Enhanced Min-delay
SmartTime now provides support for conservative minimum delay/hold-time analysis based on Fusion characterized silicon timing data. This new feature eliminates the need to over guard-band a design for minimum delay, providing a more comprehensive, precise way to perform chip-to-chip evaluation of external setup/hold and clock-to-out timing.
FlashPro v6.2
FlashPro v6.2 supports programming for the following:
- ProASIC3L: A3P600L
- ProASIC3: M1A3P250
Unless otherwise noted, these issues apply to all devices.
ProASIC3 to ProASIC3L or IGLOO migration
72815 – Device migration may not be allowed because maximum VCO Frequency is different for ProASIC3/E, IGLOO/e and ProASIC3L
Using the ProASIC3/E to ProASIC3L or IGLOO/e migration there is a check that makes sure the VCO maximum frequency is within the valid range for the target device.
The following message will be displayed:
Error: CMP435: Illegal configuration for PLL 'dpll_0/Core'.
Regenerate your PLL using the latest version of SmartGen.
The message is incorrect, and should be displayed as:
CMP449: The VCO frequency for the PLL/DYNCCC <instance name> does not fall within the allowed range for the device in use. The allowed range is minvco MHz to maxvco MHz.
Before you can continue migration, you must make sure that you modify the frequency of the ProASIC3/E design so the maximum VCO frequency falls within the valid range of the ProASIC3L or IGLOO/e devices. For more information, please refer to the ProASIC3L or the IGLOO/e data sheets.
IGLOO and ProASIC3L Flash*Freeze Flow
73424 – DRC fails after running synthesis when the ULSICC macro is used
If the ULSICC macro is instantiated, and if 'run DRC after synthesis' is on in the Configure Design Flow dialog, running the Design Rule Check (DRC) will fail with an error:
Error: Designer failed to generate files. View the Designer log file:"\designer\impl1\designer_genhdl.log" for more details. Failed
When you click on the link to open designer_genhdl.log you can see an error:
Error: CMP859: An instance of Low-Static ICC
'.../FlashFreezeCtrl_wrapper_inst/U0/FlashFreeze_FSM_inst/ULS
\ICC_INSTANCE' was found in the design. This macro is allowed only in Flash*Freeze Mode Type-2. Please specify a Flash*Freeze port in the Compile options to enable the Type-2 mode. Refer to the ProASIC3L data sheet for details on Flash*Freeze modes.
This error is generated because the Flash*Freeze port name was not specified in the design. You can discard this error since there is no way to enter this port name before running DRC.
Required user action: Disable 'Run DRC after synthesis' in the Configure Design Flow dialog if a ULSICC is instantiated in your design.
72767 – Precision v2007a.8 synthesis does not include support for Flash*Freeze
The current version of Precision synthesis does not support the IGLOO/e or ProASIC3L Flash*Freeze feature.
Workaround: Use the current version of Synplify Pro/Synplify AE 9.0.A2 supplied with Libero IDE v8.2.
SynplifyPro/Synplify AE
73447 – User needs to manually instantiate syn_noprune in the RTL w/ULSICC macro (IGLOO/e, ProASIC3L, and ProASIC3/E)
To synthesize ProASIC3/Fusion ULSICC macro, user needs to manually instantiate syn_noprune in the RTL to avoid the macro being optimized out by Synplicity. This happens in Synplicity because ULSICC does not have any output port.
A sample syntax is:
ULSICC I_ulsicc (.LSICC(LSICC_in) ) /* synthesis syn_noprune=1 */;
Libero IDE Catalog
72434 – The Cortex-M1 core is displayed in the Catalog for the ProASIC3L family; however, it is not actually available in v8.2
Using Libero IDE v8.2, the Catalog shows an M1 Core as one of the available cores for the ProASIC3L family, however this core is not actually supported in Libero IDE.
If you try to generate an M1 core, a Fusion M1 core will be selected. The generation will succeed but when Libero tries to import the M1 core to the project, you will get a pop-up message asking to change the Family, Die, and Package to a Fusion die and package.
You should click on NO, otherwise the project will be switched to the new family, die, and package.
72514A– ProASIC3L DirectCores in v8.2 will use ProASIC3/E DirectCores
DirectCores for ProASIC3L devices are not yet labeled in Libero IDE v8.2 for ProASIC3L devices. When designing with a ProASIC3L device and a DirectCore is needed, the Libero Catalog will map to the ProASIC3/E DirectCore list.
72514B – Synplify/Pro AE and Precision AE do not yet include ProASIC3L devices
The new ProASIC3L devices noted in the "What's New" section are not yet included in Synplify/Pro AE 9.0.2A or Precision 2007A8 synthesis software. The selected ProASIC3L project device will be automatically mapped by Libero IDE to the corresponding IGLOO device in the synthesis tools, for example an A3P250L project device will be seen as AGL600V2 in the synthesis tools. The correct ProASIC3L device will however be passed to Designer.
The following summarize the device mapping in the Synthesis tools:
- A3P250L: AGL600V2, STD
- A3P600L: AGL600V2, STD
- A3PL1000L: AGL600V2, STD
- A3PE3000L: AGLE600V2, STD
If you are not using Libero IDE but are using Designer, you will have to manually map your ProASIC3L design to IGLOO for synthesis.
72514C - Simulation mapping for ProASIC3L using VHDL designs
-
Using Libero IDE simulation tools (ModelSim AE)
DirectCores for ProASIC3L devices are not yet labeled in Libero IDE v8.2 for ProASIC3L devices. When using VHDL and designing with a ProASIC3L device and a DirectCore is needed, the Libero IDE Catalog will map to the ProASIC3 DirectCore list. Since the ProASIC3 cores are being used for ProASIC3L devices, Libero IDE automatically maps the ProASIC3 libraries to the ProASIC3L library. Inspecting the "run.do" file that is automatically generated by Libero IDE, you will notice the extra mapping line as follows:
vmap Proasic3 "$env(MODEL_TECH)/../actel/vhdl/proasic3l"
-
Using standalone simulation tool (non-Libero IDE supported)
In the case of using standalone simulation tools, you must manually map the ProASIC3 library to ProASIC3L for simulation if you are using VHDL and your existing design includes DirectCores. The following is an example on how to do the mapping:
vmap proasic3 "$env(MODEL_TECH)/../actel/vhdl/proasic3l"
SmartTime
72573 - Scenario parameter in export sdc causes error in TCL.
If you export an SDC file (without using SmartTime scenarios), and then export the command in a Tcl script and run the script in Designer, you will get the following error:
ERROR: Parameter -scenario is expecting a value.
ERROR: The command [export] failed with error code 0x80070057
ERROR: Failure when executing Tcl script. [ Line nn ]
To fix the problem, edit the Tcl script and remove the "-scenario" word from the respective line:
export -format "sdc" -variant "extended" -naming_level "optimized" -pin_separator ":" -scenario {./file.sdc}
The script should appear as follows:
export -format "sdc" -variant "extended" -naming_level "optimized"
-pin_separator ":" {./file.sdc}
74057 – SmartTime automatically annotates Minimum Pulse Width on ACMCLK to 10 MHz.
In Fusion designs, the recommended clocking scheme is to use the NGMUX to choose between a slow initialization clock, which is limited by the ACMCLK that has a maximum output of 10 MHz, and a Fast System Clock, which can be 40 or 80 MHz. Both clocks come from the PLL and the INIT_DONE signal is used as the Mux control.
Due to the Minimum Pulse Width annotation by SmartTime, SmartTime shows 10 MHz for both fast and slow clock domains, and this prevents the actual timing from being displayed.
Workaround: Put a False Path on the ACMCLK pin.
Designer
73415A – IBIS aborts when exporting A3PE3000L files
IBIS file export will display an error when attempting to export file for A3PE3000L for COM temperature range.
73415B – IBIS model IND temperature range is not available for currently supported ProASIC3L devices
Industrial temp range IBIS model data is not available for A3P250L, A3P600L, A3P1000L, or A3PE3000L.
