Libero IDE v8.1 Release Notes
(updated on Dec 19, 2007)
Thank you for your interest in Actel's Libero Integrated Design Environment
(IDE) v8.1.
Project Manager
- File Linking allows you to "link" your Libero IDE project to source files that are maintained in a remote location such as a design repository that is intended to be shared with other locations. You can link to HDL files (source + package files), stimulus files, and to constraint files. Any number of Libero IDE design projects or design project locations can now link to and share the same source file, which could be a company controlled IP core or an HDL block that is standardized and archived. It is no longer necessary that a source file be stored locally on the PC where the Libero IDE project is being designed. Linked files are opened in a "read only" mode, and a dialog provides opportunity to store the file locally.
- The Designer Block flow introduced prior to Libero IDE v8.1 allows you to create a unique "Designer Block", which can immediately be implemented into a design or preserved for future use. A completed block is optimized using the customary synthesis, simulation and place-and-route flows. When creating a new project in Libero IDE or Designer, select a "Block Design Flow" instead of a standard flow, after which the block can be published to a repository. Libero IDE v8.1 enhances the Designer Block flow such that you can now instantiate multiple blocks into your Libero IDE design project. You can instantiate the same block multiple times in the same design, or you can instantiate several different Designer blocks in the same design. Libero IDE created blocks can be viewed and managed within the MultiView Navigator tools.
- Core Packager/Publisher. Once a Designer Block is created, you can "publish" it to Libero's IP/Core Catalog using a new "Publish Packager" flow. The Libero IDE block creation and instantiation flows support "design and re-use" of functional blocks, saving design time and reducing time to market. A number of catalog options can be noted such as company name, version, library type, catalog name, and you can define filter parameters with which the component can be easily located in the catalog. Once published, the Block/core is visible under the "User Defined" cores in the Libero IDE Catalog.
- Simulation Options. A new, more flexible user interface is provided for selecting and providing information related to the simulation needs. This includes options for generating Value Change Dump (.vcd) files that can be used by SmartPower for more accurate power estimation.
- Tool Profiles. Tool Profiles are now user specific. Once selected, a set of profiles remains constant for all projects until modified by the user.
SmartGen
- A Flash*Freeze management macro has been added to support IGLOO devices.
This macro manages a clean entry and exit from Flash*Freeze state ensuring
the design saves state. It also hand shakes with user logic to delay
actual entry into the Flash*Freeze mode if desired. It filters user
clocks before and after actual the Flash*Freeze state to ensure that
user logic always receives clean clock signals. Clock domains requiring
state-saving during Flash*Freeze should have the clock routed through
this macro.
SmartPower
- Power Profiles. SmartPower allows you to create a power "profile" for a design. A power profile is a combination of active, standby, Flash*Freeze, or user created operational modes. You specify the amount of time (as a percent of total) the design will be in each operational mode. SmartPower calculates the total power for each mode, plus total power based on the weighted average of the power consumption of all modes. Consequently, a more realistic report of power is provided. Power profiles can be created to test different configurations in order to create an optimal design.
- Battery Life Estimator. By entering the current capacity of a specific battery, SmartPower provides the battery life based on "always active" operation, as well as for power profile scenarios. Using a power profile provides a more realistic estimation of battery life, since most battery operated applications are seldom in a full active mode all of the time.
- Clock Domain power analysis calculates and displays the power consumption for all Clock Domains in the design. This helps you visualize and potentially address specific clock domains that are responsible for excessive power consumption. Power consumption for the domain's Clock Tree and Data Path are shown in a visual dialog, including the percent contribution of the total for each.
- Peak Power Analysis. Libero IDE v8.1 provides a cycle-based (or cycle-accurate) power analysis. Based on a VCD simulation file, SmartPower will report one power value per clock period (or half-period) for a given waveform instead of a typical average power for the whole simulation. This feature allows you to easily evaluate every cycle in terms of power performance to determine the peak power. This feature is also helpful to understand and further minimize power consumption by facilitating the analysis of data-dependent power variations, as well as dynamic power variations due to clock-gating or clock frequency variations.
- Spurious Transition Analysis. SmartPower 8.1 identifies functional as well as undesirable spurious "hazard" transitions that occur during switching that all contribute to higher dynamic power consumption. Typically during a clock cycle a gate with multiple inputs experiences multiple hazard transitions before settling to the correct logic level. SmartPower 8.1 analyzes the transitions that occur during each clock cycle and a report displays all hazards and respective power consumption associated with each net. A comprehensive user interface dialog allows the user to specify the nets and number of cycles to be reported.
- Data Change Report. This new report lists specific data and other changes that have occurred in the software over time. A reference number and topic summary are shown. Contact Tech Support for more information on the subject.
SmartTime
- Constraint Wizard. A new wizard for creating timing constraints guides you to easily set up the specific constraints for your design. Page-by-page dialogs with graphical aids assist you to understand and set constraints for overall/explicit clocks, I/O requirements or specific clock delays with minimum/maximum input and output delays, generated clocks, and input and output pin clock requirements. A summary dialog allows you to confirm all selections made.
- Constraint Scenarios. You can now set up, save, and test timing constraint "scenarios" to help you better understand the timing capability and performance of your design. When going into a constraints scenario dialog, you can create a set of constraints that can be used to analyze your design pre-layout, and/or to drive timing driven place-and-route. Multiple constraint scenario dialogs can be open simultaneously to allow you to easily view the constraint sets that are to being tested. Both Layout and SmartTime Options allow for selection of saved scenarios, plus you can import an SDC file into a specific scenario, or export a selected scenario with an SDC file.
- Constraint Coverage Report. SmartTime provides statistical data on the actual constraint tests that are performed. The report shows the number of constraints that are met, not met, or are untested. Supported checks are: setup, hold, recovery, removal, and output. Adjustments can then be made in SmartTime to ensure that more constraints are tested and met.
- New TCL commands. 44 new TCL commands have been added. See on line help or the User Guide for the complete listing.
- Data Change Report. This new report lists specific data and other changes that have occurred in the software over time. A reference number and topic summary are shown. Contact Tech Support for more information on the subject.
SmartDesign
- Bus Support. SmartDesign supports instantiation of AMBA based DirectCores including bus cores such as Core AI, CoreAPB, CoreAHB, CoreAHB2APB, and more. Simply locate the AMBA bus or AMBA bus DirectCore peripheral core in the Libero IDE Catalog and drag it onto the canvas. The Canvas is also enhanced for bus related SmartDesigns for auto and relative placement of busses, special symbols, rotation, flipping, and more.
- Connectivity Check. A new Connectivity Check grid is added into SmartDesign. Using this new Connectivity Check grid, SmartDesign displays connectivity violations under a new field called "Message" field. The Message field helps you identify the violations by displaying an icon to indicate if the message is an error or a warning, along with descriptions of the error/warning. Correct your connection violations in the Connectivity Check grid as needed to complete you SmartDesign component.
- HDL Components. HDL components are created from HDL modules present in the Libero IDE Design Hierarchy. HDL components are now explicit components showing status icons and tool tips. You can now create an HDL component by right-clicking on the module from the Libero Design Environment without having to drag-and-drop onto a SmartDesign canvas.
MultiView Navigator
- Routing View for Axcelerator devices. The MultiView Navigator now shows the "Route" view of the design in addition to the "Ratsnest" view. The "Route" view is only available after place-and-route is complete. In this view, you can see a representation of the routing segments used in the design. You can use the Display Settings dialog box from the View menu to change the default color schemes that are used to display the routing segments.
- Reserve Pins. This feature allows you to reserve a package pin that will not be used in the current design, and it is expected that the design will be used in a revision of the design in the future. An example is when you begin a design with a larger device that you intend to implement later in a smaller device. Because there may be pins on the smaller device that are not bonded, you want to be sure that the pin assignments created on the larger device are compatible with the pins on the smaller device. This feature reserves the pins on the larger device that are not bonded on the smaller device. Pins in the current device that are not bonded in the target device will be marked as "reserved". You can explicitly reserve a pin in the PinEditor, I/O Attribute Editor, or by importing a PDC constraint file with the "reserve" PDC command.
Designer Layout Options
- Power Driven Layout. A "Power Driven Layout" Option drives placement of the design based on an imported simulation Value Change Dump (VCD) file, or SmartPower’s
design analysis data. With little to no impact on timing of the design,
the PDL flow dynamically guides placement of the physical layout of
IGLOO, Fusion, and ProASIC3 designs to achieve the lowest possible
power consumption for low power and portable applications. If timing
of the design is of concern, Actel recommends running Timing Driven
Place-and-Route first and check the timing results. If the timing is
met, then re-run layout using power driven layout, and re-check timing.
If low power consumption is the main concern, run Timing Driven Place-and-Route
and Power Driven Layout simultaneously. There is small run-time cost
when using power driven layout.
- Multi-pass Layout. The Multi-Pass Layout configuration has been significantly enhanced to correct ambiguities of the previous version and add new features. Enhancements are:
- Specify a starting seed index
- Select Minimum Delay timing violations to compare layout results
- Select Total Negative Slack as a measurement criterion in addition to Worst Slack, or the frequency of the slowest clock, or a specified clock
- Stop or not stop on first pass without violations
- File name conventions are changed to avoid/eliminate confusion
- <adbFileName>_timing_r<runNum>_s<seedIndex>.rpt
- <adbFileName>_timing_violations_max_r<runNum>_
s<seedIndex>.rpt
- <adbFileName>_timing_violations_min_r<runNum>_
s<seedIndex>.rpt
- <adbFileName>_iteration_summary.rpt
- <adbFileName>_r<runNum>_s<seedIndex>.adb
- Improved summary report provides detailed and clear results
CoreConsole v1.4
- CoreConsole v1.4 adds support for updating your IP database from the Actel web-based IP repository. CoreConsole can now seamlessly detect, download, and install new or updated IP cores that are published in the Actel web based IP repository. Now you can remain up to date with the latest Actel DirectCore IP CCZ releases simply by running CoreConsole. By default, CoreConsole will check for new or updated IP core CCZ files in the Actel web-based IP repository at startup, alert you to any available IP for download, and guide you through the selection, download, and installation process. IP core updates can also be fully automatic, so that new IP core releases are automatically downloaded and installed in the background without any user intervention. New or updated cores acquired in this way are available for immediate use in CoreConsole and the Libero IDE catalog. CoreConsole's Actions > Change Versions can be used to update existing designs to use updated IP cores. The CoreConsole IP update mechanism can be configured by using the Options > System Options dialog box and clicking the Updates tab. CoreConsole is not included in the Libero IDE software download and must be downloaded separately. View the complete CoreConsole 1.4 release notes and download CoreConsole v1.4.
SoftConsole 2.0
New Devices
| Device |
Package |
Speed Grade |
Temperature Range |
| A3PE3000 |
FG484 |
STD, -1, -2 |
COM, IND |
| -F |
COM |
New Packages
The following new IGLOO packages are available.
| Device |
Package |
Speed Grade |
Temperature Range |
| AGL030v2 |
µCS81 (4x4) |
STD, -1 |
COM, IND |
| AGL030v5 |
µCS81 (4x4) |
STD, -1 |
COM, IND |
| AGL600v2 |
CS281 |
STD |
COM, IND |
| M1AGL600v2 |
CS281 |
STD |
COM, IND |
| AGL600v5 |
CS281 |
STD |
COM, IND |
| M1AGL600v5 |
CS281 |
STD |
COM, IND |
Package Updates
The following devices have package updates as noted.
| Device |
Package |
Re-compile required? |
| AFS600 |
PQ208, FG256, FG484 |
Yes |
| M1AFS600 |
| M7AFS600 |
Device Updates
A3P030, AGL030V2, AGL030V5 .adb invalidation. All existing .adb files for these devices will be invalidated and put back to pre-compile state. Designs must be re-compiled and re-run through place-and-route using v8.1. Any constraints should be saved and imported into the project.
A3PE3000 .adb invalidation. All existing .adb files for the A3PE3000 will be invalidated and put back to pre-compile state. Designs must be re-compiled and re-run through place-and-route using v8.1. Any constraints should be saved and imported into the project.
New Programming File Generation Support
Updated PDB/STAPL file generation. Previously generated programming files for the following devices must be regenerated using this v8.1. FlashPro v6.1 included with Libero IDE v8.1 is required for device programming.
- AFS250, AFS600/M1AFS600/M7AFS600, AFS1500
- AGL600/M1AGL600
Programming File Generation is enabled for the following devices:
- AGL030
- M1AGL600
- A3P030
- M1A3P600
- M1A3PE600
- M1A3PE1500
FlashPro v6.1
FlashPro v6.1 provides PDB/STAPL generation and programming for all above stated devices where programming file generation is enabled.
ProASIC3 to IGLOO Design Migration
A migration wizard is available to assist you in converting an existing A3P design to a compatible device/package IGLOO design. After layout has been run and an adb has been created in Designer for your A3P design, go to Tools > Setup, and select IGLOO (or IGLOOe) as the migration family. You must first confirm that the desired IGLOO device and package is supported in the Libero IDE/Designer software. If the IGLOO device/family is not yet available in the software, you will get a message saying that there is no compatible die/package available.
- Synplicity Synplify/Synplify Pro AE 9.0a1
- Re-designed and enhanced user interface
- Operating Conditions Support
- ProASIC3: COM, IND, MIL, TGrade 1 and TGrade 2
- ProASIC3E: COM, IND
- Fusion: COM, IND
- IGLOO: COM, IND
- Axcelerator: COM, IND, MIL
- See Synplify/Synplify Pro AE 9.0 release notes for more information
- Mentor Graphics ModelSim AE 6.3c
- SynaptiCAD WaveFormer Lite 11.14a
- Actel ViewDraw
- Actel FlashPro v6.1
- Actel Silicon Explorer v5.2
The following software tools are all included in the Libero IDE v8.1 Windows DVD and individually available for download from Actel.com:
Support on Windows 2000 and Linux RedHat 3.0 ends with Libero IDE v8.1.
Disk ID license versions of Libero IDE run on Windows Vista. Full Windows Vista support is planned for Q2 2008.
For more information, view the complete System Requirements.
Libero IDE v8.1 requires a current Libero IDE v8.0 license. Register for a free Libero IDE Evaluation or Gold license, or contact your local Actel Sales office to purchase a Libero IDE Platinum license.
Unless otherwise noted, these issues apply to all devices.
72268 – Installation of Libero IDE v8.1 web download version adds "Libero 8.1 Beta" to the Start Programs Menu. There is no Beta software installed. The Libero IDE v8.1 software that is installed is an official production release. The "Libero 8.1 Beta" text that is added to the Start Programs menu should be deleted by right clicking on the text, and selecting "delete". This added text only occurs in the web download version of Libero IDE v8.1.
72423 – Libero IDE Linux installation menu shows incorrect Synplify AE and ModelSim AE versions to be installed. When installing Libero IDE Linux v8.1, the Installed Tools Selection list shows Synplify Pro AE v8.8.a1 and ModelSim AE 6.2G will be installed. This text shows the incorrect version number for these tools. Synplify Pro AE 9.0a1 and ModelSim AE 6.3c will actually be installed.
Project Manager
70292 – Behavioral HDL file cannot be found in the Libero Hierarchy
71488 – Buffer overflows when the parser can not find closing _include statement. If a Verilog include statement does not have a closing character " (example: 'include "debug_variables.v; ) you get the following assertion:
Error: Internal Error:
Assertion Failed in "M:/prod80_all/afi/lib/base/src/sys/sysfil.c",
line 1322.
Required user action:
Correct the typo and add the closing " char at the end of the include statement.
Synplify
68237 – Synplify Utilization Report (.srr) error (v8.8a1) (APA, A3P/E)
70291 – Can not set constraints on clocks in and out of PLLs
70604 – Synplify writes out SDC clock constraints even for auto-constraints
Scenario Starting in Libero 8.0 (Synplify 8.8A1), Synplify will write out SDC clock constraints including default synthesis constraints. User constraints take higher priority, but the default constraints will also show in the SDC file.
68192 – Synplify 8.8a1 expands tile count/area requirements for CoreI2C DirectCore (VHDL).
Workaround: Turn off the FSM compiler. Synplicity recommends using attributes in the RTL code so that the FSM compiler is only turned off for CoreI2C and the rest of the design can be fully optimized. This is not possible with obfuscated code; however, you can only turn off the FSM compiler from the GUI.
71663 – CoreWatchdog IP Core in VHDL 16-bit mode does not work due to erroneous logic created by Synplify (8.8a1).
Workaround: Use 32 bit mode.
Simulation
72698 – ModelSim AE 6.3C will not run simulation when license is based on USB or Parallel Port Dongles. Mentor Graphics made a change in their ModelSim 6.3 software that specifically looks for lower case alpha characters in the FlexID 9- number of the USB license feature lines. Customers with USB licenses generated prior to 12/3/2007 found that ModelSim 6.3c would not work with their license, while ModelSim 6.2 would. As of 12/6/2007, all USB licenses that included alpha characters in the dongle id feature line were regenerated to provide lower case alphas and re-sent to the registered users.
Parallel port dongle licenses were also affected. Parallel port dongle licenses, however, do not have to be regenerated, but they must utilize a MacroVision clean up utility and a newer FlexID-8 driver must be downloaded/installed. The clean-up utility and driver are available from Actel's website:
- Download and run the MacroVision Flexid Clean-up Utility
- Download and install an updated MacroVision Flex-ID 8 driver. During the install, be sure to check the "FLEX-ID 8" driver installation option.
ModelSim 6.3 will run with an existing license after the utility software is used and the updated driver is installed.
68648 – Simulation error when a Fusion SmartGen netlist generated from Libero IDE 8.1 or newer is simulated with an older version of ModelSim
63562 – FIFO flag does not work if the read/write port widths are different (A3P/E, IGLOO/e, AFS)
SmartDesign
63492 – Performing Drag and Drop of multiple components from Design Explorer
64629 – Page number in Status bar is not updated when "Allow page splitting" is OFF
65222 – Connectivity Grid column resizing behavior
65266 – Outputs are referred to as Inputs in DRC message when generating component
65538 – "Error: left and right values of bus 'IN2' can not be equal." SmartDesign does not support the legal VHDL syntax: std_logic_vector(0 downto 0)
67187 – Buses of different widths in Bus Interfaces (BIF) are reversed when connected
71457 – Nets with multiple drivers are not flagged. Any net in a SmartDesign must have only one driver. SmartDesign may not always flag a net that has multiple drivers when the Connectivity Check is done, and the error will not be noted until Synthesis is run. Synthesis displays the following:
ERROR: Net "net_name" in work. has multiple drivers
Workaround: Open the SmartDesign, disconnect unnecessary drivers for the net, and keep only one driver.
70293 – Connections are hidden if the instances are too close together
SmartGen
67614 – Failed to load the STAPL file which contains FlashROM with the same region names (A3P/E)
Block Creation
70156 – Designer Block is exported twice when being published
SmartTime
54900 – Designer quits when executing the st_restore script command
Designer
72166 - Incorrect output drive strength for the IGLOO AGL030. The 2X output drive strength selection only provides 1X drive strength on LVTTL I/Os due to a software issue that causes incorrect configuration of the I/O. This will be resolved in the next Libero IDE/Designer service pack.
Designer Programming File Generation
72168 – Libero IDE/Designer v8.1 SVF programming file is not correct for the IGLOO/e and ProASIC3/E devices. Programming these devices using an SVF file generated by Libero IDE/Designer v8.1 will cause programming to fail.
Workaround: Use either STAPL or PDB programming file generation. This issue will be resolved in the next available Service Pack.
