Unless otherwise noted, these issues apply to all devices.
Synplify/Synplify Pro AE
68465 – AX and RTAX-S Timing in Synplify AE 8.8A1
Synplify/Synplify Pro AE version 8.8A1 includes incorrect CLKINT timing values. Designs are functionally correct however timing constraints can not be met. This issue is resolved in Synplify/Synplify Pro AE version 8.8A2. Download Synplify/Synplify Pro AE 8.8A2.
Synplify License Server
66292 – Libero IDE Windows floating license servers need to be re-started with new synplctyd
- Stop the license server prior to installing Libero IDE. This is necessary to allow c:\synlm\synplctyd to be updated.
- Install Libero IDE v8.0
- In the Flexlm license manager in the System Control Panel, change the path to the DAEMON as shown: c:\synlm\synplctyd
The synlm folder is installed automatically to your C drive during the Synplify installation.
Do not change the license.dat file.
- Restart the license manager
For more information see the Synplicity Licensing Guide in the synlm folder on your C drive.
Project Manager
64609 – Synplify DSP .dat files are not copied to the simulation folder
The .dat files required to run the simulation for a component generated by SynplifyDSP are not copied to the simulation/ sub folder of the project. As a consequence the post synthesis simulations fail.
Workaround: Manually copy the .dat files from the SynplifyDSP implementation to the simulation folder of the project.
64454 - CheckHDL is a syntax checker only, not a synthesis checker.
For example, RTL syntax allows a parameter that is not defined and Check HDL will correctly report 0 errors, but the synthesis tool may fail. A future release will have an additional option for synthesis checking.
65787 – Use CoreConsole in the full GUI mode to configure an IP core that has an APB/AHB interface.
65478 – Single bit bus in port name creates a mismatch between post-synthesis VHDL netlist and source file. Single bit busses in VHDL are renamed by Synplify. For example "in std_logic_vector (0 downto 0);)" is changed to "\example[0]\". This prevents post-synthesis and post-layout simulation from working. Modify the top level and avoid the single bit bus in the port name.
65995 - Do not rename a package that contains a module instantiated into SmartDesign. If you instantiate in SmartDesign a module defined in a VHDL package you should not rename the package. SmartDesign is not aware of the new name and the original package name will be exported in the VHDL netlist.
66581 – Project Manager programming file type STAPL setting is not honored by Designer. Checking "Use STAPL File" option for FlashPro's programming file type using the Libero IDE Project Manager, select Project —> Settings —> Flow, is not recognized by Designer. Designer will generate a PDB file by default. If a STAPL file is needed, you must be manually select the STAPL generation checkbox in Designer's Program File Generation dialog.
67562 - "Simulation files" appear in multiple places in the File Manager. To support SmartDesign and Designer block flow, Components and Modules are added to the Hierarchy and Files tabs of the Design Explorer. On the Files Tab, each generated component may have its own simulation files, stored under that component as "Simulation Files". A DirectCore IP core consists of the core plus a core wrapper; for each DirectCore you will see two simulation files. You need not be concerned about the Simulation files that are maintained under a Component. The simulation files that ModelSim uses are under User Files/Simulation Files.
64605 – Testbench name created by Synplify DSP is different from WaveFormer Lite Testbench Name
66045 – Block Creation Flow: Opening a block created in Libero IDE v7.3 causes an error when opened using Libero v8.0
65974 – Can not instantiate a user created block that was generated prior to v8.0
65999 – Project must not be created in the same location as a CXF or CCP file
66327 – Packages used in the testbench are not passed to ModelSim for post synthesis simulation
66322 – ModelSim may generate errors using Components generated from Catalog DirectCores
Project Manager/CoreConsole
CoreConsole v1.3 software is not installed with the Libero IDE v8.0 suite. It must be downloaded and installed separately.
After installing CoreConsole open the Project Manager in Libero IDE. From the toolbar select, Project —> Profile, add a Core Configurator/CoreConsole 1.3 profile and browse to the CoreConsole.exe, located by default at C:\CoreConsole_v1.3\bin\CoreConsole.exe or the user selected location. CoreConsole and Libero IDE must reside on the same PC to utilize the integrated tool flow.
64800 – CoreConsole and Libero IDE must reside on the same PC to utilize the integrated tool flow.
Use Libero IDE v8.0 with CoreConsole v1.3. It will not work with previous releases of Libero IDE.
IP DirectCores in the Libero IDE Project Manager Catalog may not be current versions. The versions of the IP cores shown in the Project Manager catalog are those that were resident in your CoreConsole v1.3 installation. Check the website at http://www.actel.com/products/software/coreconsole/IPcores.aspx for the availability of new or updated IP cores, which can be imported into CoreConsole. By default, the most current version installed with CoreConsole is shown in the Catalog IP listing. You can view older versions that are also available in CoreConsole 1.3 by going to Libero —> Project —> Preferences, select the "Advanced" tab, and un-checking the "Display only the latest version of the core" checkbox. The version numbers of the cores will be displayed for each IP core. You should always use the latest version of an IP core for new designs.
Release notes and Handbook for IP DirectCores are not accessible from the IP Catalog in the Project Manager. Refer to the DirectCore Handbook and release notes before configuring a DirectCore. These documents are not available via the IP Catalog. To access the datasheet or release notes for a DirectCore IP, launch CoreConsole by clicking the CoreConsole button in the Design Entry Tools section of the Project Manager.
DirectCore configurations from the Project Manager are not validated. For many DirectCores available in the IP catalog, there is no check to verify the configuration selections are valid. An improperly configured core can be generated, but will fail synthesis. Always refer to the core Handbook before configuring a DirectCore. To access the Handbook or release notes for a DirectCore IP, you need to launch CoreConsole by clicking the CoreConsole button in the Design Entry Tools section of the Project Manager.
CoreConsole generation of an IP core will not occur if a PDF document is open. For example, if you have a DirectCore PDF Handbook open, generation of the component will not occur. You must close all PDF documents before you can generate the component.
65878 - Ignore "Bus interface…" warning when the CoreConsole subsystem is imported.
When importing a CoreConsole subsystem through a CXF file, SmartDesign may generate the following warning message about Bus Interface problems:
"WARNING: Bus interface 'bus_name' of type 'bus_type' could not be added to module 'module_name.' Please check that the definition type is available in the bus definition catalog."
This message can be ignored.
64802 – Do not include more than one M7 core in a Libero IDE Project.
Actel devices that accommodate an M7 core will only accept one core, however there is no warning in Libero if you include more than one M7 core in a project design. Instantiating more than one CoreMP7 in a project, even if only one CoreMP7 is instantiated in the Top, will mix up the CoreMP7 common files and running simulation may not correctly make use of the user-defined transactions from the BFM files. A design with multiple M7 cores could succeed through the Libero IDE/Designer design flow, however would error upon program file generation.
View CoreConsole v1.3 Release Notes.
SmartGen
68324 – You can not create a symbol from a component generated by Smartgen v8.0.
This feature was available in previous versions of SmartGen and is a bug in Libero and Designer v8.0.
- Go to the Hierarchy Tab in the Design Explorer Window
- Switch from the Component View to the Module View => Right click and Create Symbol will be available, there but you still get an error if you try to generate a symbol
Workaround:
- Import as an 'HDL source' the HDL file generated with the component => Now the module is defined twice so pick its definition from the file located under <project>/hdl
- Right click on the selected HDL file and create the symbol
- You should not get the error message and the symbol is created
67731 – FlashPro error in programming due to duplicate region names in FlashROM (A3P/E, AGL/E, AFS)
When using copy/paste in SmartGen FlashROM (FROM) interface to populate RAM contents, the cell name in Properties (e.g. Region_7-15) should change accordingly and properly reflect a unique region name. SmartGen may duplicate a region name using copy/paste. SmartGen allows this duplication of region names, but FlashPro will error during programming of the device.
Workaround: Region names must be unique. If a duplicate region name is created by SmartGen, manually change the "Name" under the Properties display.
67046 – SmartGen reports incorrect clock delay of 921 ps for the delayed clock macro for IGLOO/e families when user selects hardwired I/O as the input clock source. The correct delay is 470 ps.
This is fixed in v8.0 SP1.
65535 – SmartGen generated RTL behavioral model files are not shown in the Hierarchy tab.
These files are viewed in the "Other Files" category in the Files tab under components. To use the behavioral HDL model, import it into Libero IDE as user HDL.
SmartDesign
65900 – Error: The Component <SmartDesign_Block_Name> needs to be generated.
This synthesis error occurs when a SmartDesign block has a component that has not been generated or regenerated after a change. Update or regenerate the changed component then Generate and rerun synthesis.
63764/67275 – You can not instantiate a ViewDraw Schematic component into SmartDesign. In order to include a ViewDraw file into SmartDesign, you must first convert it to HDL, and then import the HDL into Libero IDE as user HDL.
63919/67276 – Net names are not shown in the SmartDesign Schematic View. Use the Connectivity Grid Net-to-Instance view to view the net names. Net names in the Schematic view will be available soon.
65170/67277 – Import of a previously generated SmartDesign component does not include its instantiated components.
In order for an HDL module (or entity) to be instantiated into SmartDesign, a component of that module (or entity) must exist first. An HDL module (or entity) is not a component by default. When an HDL module is instantiated into a SmartDesign component, a component wrapper for that module is automatically created.
If you import a SmartDesign component from one Libero IDE design project to a new Libero IDE design project, then only the SmartDesign-level instances are imported, not the underlying components. You must import all components instantiated in the just-imported SmartDesign component in order to resolve/restore the complete SmartDesign design component.
In the case of any HDL module that is instantiated in the SmartDesign component, there is no component to import. You must first import the HDL file. Because the HDL 'component' is not automatically created, you need to manually force the HDL component to be created by instantiating. To minimize rework on the imported SmartDesign component, use a temporary SmartDesign component.
Workaround in Libero IDE v8.0:
- Import the SmartDesign
- Import all of its instantiated components
- Import all instantiated HDL
- Create a SmartDesign named 'temp' (or any temporary name)
- Drag the appropriate HDL modules into the 'temp' SmartDesign window.
- Open up the imported SmartDesign; right click on the HDL instances and replace/repair the HDL with the HDL components as appropriate.
- Delete the 'temp' SmartDesign component.
65538/67278 – You can not promote a port to Top that is defined as "std_logic_vector (0 downto 0)".
Workaround: In the SmartDesign menu, create a scalar top-level port using Add Port from the Logic entry and manually connect the instance pin to the top-level port.
65647/67279 – Right-click menu selections for "Update and Replace" are not available if the Instance Field is not the first field in the Connectivity Grid.
Workaround: Use the right-click menu from the Canvas View, or move the Instance Column to be the first (left-most) field on the Connectivity Grid.
65830/65282 – Undo feature does not handle inverted ports or pins. If you invert a top level port, delete it, and then select "Undo", the port is returned but it is not inverted. Similarly, on an instance, if you invert pins, and then delete the instance, "Undo" will recover the instance but the inverts are lost.
65837/67283 – Update/Replace of an instance does not preserve previously inverted ports.
Workaround: Re-invert ports as needed following an update.
65832/67284 – User must manually update a component after modifying the Verilog include file. Updates to the Verilog include file do not report the component as out-of-date. Users must monitor changes in the include Verilog files and update all affected files accordingly.
65863/67285 - Update of component does not preserve the instance slice connections or inverters placed on the slice. If changes have been made to the instance after generation and the component needs to be updated, the previous connections made on a slice, and inverters implemented on ports of the slice are lost.
65913/67288 – HDL type symbol on an instance disappears. After importing an HDL netlist, instantiating it in SmartDesign, modifying the HDL netlist ports in the text editor and updating the instance, the component type symbol on the instance disappears. This missing symbol has no adverse effect on the SmartDesign component. The instance will generate properly and the HDL type is in effect.
65758 – Drag/Drop placement of instance(s) on Canvas is not ideal
Workaround: Manually rearrange the instances on the Canvas by left click and hold on the instance and dragging to a better location.
67563 – Must have port name on Top to match slice in SmartDesign. When slicing a bus with the intent to connect it to Top (for example [7:4] out of [7:0]), you must put a new port name on Top [7:4] or [7:0] will still be connected to Top and Top does not get the slice.
Workaround: Add a new port to Top x[7:4].
Compile
66526 – Design fails to compile in v8.0 that previously compiled in v7.3 SP1 (AX Devices))
Layout
65422 – Layout incremental options must be explicitly set each time
SmartTime
65868/67289 – For APA and SXA devices, importing SDC with post compile or back-annotated netlist names on the buses reports an error. The workaround is to modify the SDC names to match the original netlist names.
66726/67295 – For the SXA family the Constraints checker incorrectly reports an error when a load constraint is set on a bus. This error can be ignored.
65525a/67296 – Correct Data Source for RTAX250S is "Silicon Verified". The SmartTime report includes if the Data Source is "Advanced", pre-silicon estimates, or "Silicon Verified", validated on silicon. For the RTAX250S, the Data Source incorrectly states "Advanced".
66042/67297 – The IOREG delay for IGLOO/e 1.2v devices always shows 0 ns. This will be fixed in v8.0 SP1.
66064/67298 – Constraint checker incorrectly reports an error if output load value equals zero. Ignore this error. This does not affect delay calculation. 0 is a legal value for the output load and will be handled correctly.
65916/67300 – Clock names are not validated during SDC import. In SmartTime, if you enter a clock name with spaces an error is reported. However, when importing an SDC constraint with spaces in the clock name, there is no error check. The error is flagged later, when you open the constraint file.
65344/67301 - Min delay error messages during SDC import are misleading. The error message incorrectly reads "max" delay.
66404/67302 - SDC import allows clock constraint on a wrong pin or port (mismatched case). SDC import of clock constraints allows non-existing pins or ports to be clock sources. Any mismatch in names, including case, is accepted. The SDC reader in Libero/Designer v8.0 is now case-sensitive. The design will pass compile, and the timing report will report the constraint but the clock domain name will be missing for that particular pin/port.
66780/67303 – IGLOO/e IBIS export reports an error if the design includes LVCMOS33.
Updated IGLOO/e IBIS models can be downloaded.
SmartPower
65525b – Correct Data Source for RTAX4000S is "Advanced". The SmartPower report includes if the Data Source is "Advanced", pre-silicon estimates, or "Silicon Verified", validated on silicon. For the RTAX4000S, the Data Source incorrectly states "Silicon Verified".
66549/67305 – For AGL030, "Typical" is the only valid selection in the Power Preferences Dialog.
Ignore other options.
Program File Generation
66622 – Security level may be incorrect and must be manually checked and corrected.
Exported TCL scripts will generate Medium security instead of HIGH security.
Workaround: Manually correct the exported script by replacing the one parameter '-security_level' with these 3:
'-fpga_security_level'
'-from_security_level'
'-efm_security_level'
A second problem occurs where the generated STP file is correct, but the ADB and PDB files incorrectly have Medium security level.
Workaround: Same as above. Manually correct the exported script by replacing the one parameter '-security_level' with the 3 listed.
Alternately, you can fix the security settings in the GUI.
Designer: Open ADB and reset security settings.
FlashPro: Load the PDB. Open FlashPoint and reset the security level.
This is fixed in Libero IDE/Designer v8.0 SP1.
66696 – Use PDB file for programming when Nonvolatile Memory (NVM Flash Memory) is used and CFI client is present. (Fusion/AFS devices)
When a Fusion device is programmed using a STAPL file that contains a CFI NVM client, programming will succeed, however, NVM verification will always fail. Programming Data Base (PDB) files are not affected by this issue. When using a PDB file, both programming and verification will work successfully.
FlashPro 6.0
66462 – Nonvolatile Memory (Embedded Flash Memory) cannot be modified in PDB files generated for M7AFS600
66326 – Do not change the name of the PDB (Programming Data Base) file created using Designer's FlashPoint.
Use different Designer Views to manage multiple programming files and different file names.
Device Support
66319 – PLL may not be used in AX2000-CQ256
Libero/Designer Linux or Solaris
62382 – On-Line Help browser requirements for Linux and Solaris OS:
Linux:
- Firefox 1.5 (2005)
- Mozilla 1.5 (2003)
Solaris:
64938 – Wind/U Startup Error Message
